參數(shù)資料
型號： MCZ33991EG
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Gauge Driver Integrated Circuit
中文描述： 儀表驅(qū)動(dòng)集成電路
文件頁數(shù)： 16/36頁
文件大?。?/td> 481K
代理商： MCZ33991EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
33991
TIMING DESCRIPTIONS AND DIAGRAMS
COMMUNICATION MEMORY MAPS
These bits are
write-only
.
P0 12—This bit must be transmitted as logic[0] for valid
commands.
P0 11: P00—Desired pointer position of Gauge 1.
Pointer positions can range from 0 (000000000000) to
position 4095 (111111111111). For a stepper motor requiring
12 microsteps per degree of pointer movement, the
maximum pointer sweep is 341.25
°
.
Gauge Return to Zero Register (RTZR)
SI Address 100—Gauge Return to Zero Register (RTZR),
provided in Table 7, is written to return the gauge pointers to
the zero position. During an RTZ event, the pointer is
returned to zero using full steps where only one coil is driven
at any point in time. The back ElectroMotive Force (EMF)
signal present on the non-driven coil is integrated; its results
are stored in an accumulator. Contents of this register’s 15-
bit RTZ accumulator can be read eight bits at a time.
A logic [1] written to bit D1 enables a Return to Zero for
Gauge 0 if D0 is logic [0], and Gauge 1 if D0 is 1, respectively.
Similarly, a logic [0] written to bit D1 disables a Return to Zero
for Gauge 0 when D0 is logic [0], and Gauge 1 when D0 is 1,
respectively.
Bits D3 and D2 are used to determine which eight bits of
the 15-bit RTZ accumulator are clocked out of the SO register
as the 8 MSBs of the SO word. See Table 12. This feature
provides the flexibility to look at 15 bits of content with eight
bits of the SO word. This 8-bit window can be dynamically
changed while in the RTZ mode.
A logic [00], written to bits D3:D2, results in the RTZ
accumulator bits 7:0, clocked out as SO bits D15:D8
respectively. Similarly, a logic [01] results in RTZ counter bits
11:4 clocked out and logic [10] delivers counter bits 14:8 as
SO bits D14:D8 respectively. A logic [11] clocks out the
same information as logic [10]. This feature allows the master
to monitor the RTZ information regardless the size of the
signal. Further, this feature is very useful during the
determination of the accumulator offset to be loaded in for a
motor and pointer combination. It should be noted, RTZ
accumulator contents will reflect the data from the previous
step. The first accumulator results to be read back during the
first step will be 1111111111111111.
Bits D12:D5 must be at logic [0] for valid RTZR
commands.
Bit D4 is used to enable an unconditional RTZ event. A
logic [0] results in a typical RTZ event automatically stopping
when a stall condition is detected. A logic [1] results in RTZ
movement, stopping only if a logic [0] is written to bit D0. This
feature is useful during development and characterization of
RTZ requirements.
The register bits in Table 7 are write-only.
RZ12:RZ5— These bits must be transmitted as logic [0] for
valid commands.
RZ4—This bit is used to enable an unconditional RTZ
event.
0 = Automatic Return to Zero
1 = Unconditional Return to Zero
RZ3:RZ2— These bits are used to determine which eight
bits of the RTZ accumulator will be clocked out via the SO pin.
See Table 8.
RZ1—Return to Zero commands the selected gauge to
return the pointer to zero position.
0 = Return to Zero Disabled
1 = Return to Zero Enabled
RZ0—Gauge Select: Gauge 0/Gauge 1selects the gauge
to be commanded.
0 = Selects Gauge 0
1 = Selects Gauge 1
GAUGE RETURN TO ZERO CONFIGURATION
REGISTER
SI Address 101—Gauge Return to Zero Configuration
Register (RTZCR) is used to configure the Return to Zero
Event. See Table 9. It is written to modify the step time, or
rate; the pointer moves during an RTZ event. Also, the
integration blanking time is adjustable with this command.
Integration blanking time is the time immediately following the
transition of a coil from a driven state to an open state in the
RTZ mode. Finally, this command is used to adjust the
threshold of the RTZ integration register.
The values used for this register will be chosen during
development to optimize the RTZ for each application.
Various resonance frequencies can occur due to the
interaction between the motor and the pointer. This
command permits moving the RTZ pointer speed away from
these frequencies.
Bits D3: D0 determine the time spent at each full step
during an RTZ event. The step time associated with each bit
Table 10. Return to Zero Register (RTZR)
Address: 100
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Write
0
0
0
0
0
0
0
0
RZ4
RZ3
RZ2
RZ1
RZ0
Table 11. RTZ Accumulator Bit Select
D3
D2
RTZ Accumulator Bits To SO Bits
ST15:ST8
0
0
[7:0]
0
1
[11:4]
1
0
[14:8]
1
1
[14:8]
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