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參數(shù)資料
| 型號(hào)： | MK74ZD133Y |
| 英文描述： | PLL and 32-Output Clock Driver |
| 中文描述： | PLL和32個(gè)輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | MK74ZD133Y |
MK74ZD133
PLL and 32-Output Clock Driver
PRELIMINARY INFORMAT ION
MDS 74ZD133 C
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
3
Revision 010899
Printed 11/17/00
Number
1, 2, 9
3, 10, 16, 22, 27
4
5
6, 7,28,29,35,36,50,55
8
11, 12, 14, 15
13
17, 18, 20, 21
19
23
24
25, 26
30, 31, 32, 33, 37, 38 OUT15-OUT20
34, 39, 45, 51
40, 41, 43, 44
42
46, 47, 48
49
52
53
54
56
Name
Type
O
P
I
I
P
O
O
P
O
P
P
I
O
O
P
O
O
O
I/O
I/O
I/O
I/O
I/O
Description
Clock outputs 1, 2 and 4.
Connect to ground.
Clock input for reference.
Feedback input for "zero delay" in Multiplier Mode.
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
Clock output 3. Connect to pin 5 for Zero Delay Mode.
Clock outputs 5 through 8; level set by VDD5:8 on pin 13.
Power supply for outputs 5 through 8. Cannot exceed VDD.
Clock outputs 9 through 12; level set by VDD9:12 on pin 19.
Power supply for outputs 9 through 12. Cannot exceed VDD.
Power supply for outputs 13 and 14. Cannot exceed VDD.
Output Enable. Tri-states all clock outputs when low. Internal pull-up.
Clock outputs 13 and 14; level set by VDD13:14 on pin 23.
Clock outputs 15 through 20.
Connect to ground.
Clock outputs 21 through 24; level set by VDD21:24 on pin 42.
Power supply for outputs 21 through 24. Cannot exceed VDD.
Clock outputs 25 through 27.
Clock output 28 and output frequency select 0 per table on page 5.
Clock output 29 and output frequency select 1 per table on page 5.
Clock output 30 and output frequency select 2 per table on page 5.
Clock output 31 and output frequency select 3 per table on page 5.
Clock output 32 and output frequency select 4 per table on page 5.
OUT1, 2, and 4
GND
CLKIN
FBIN
VDD
FBOUT3
OUT5-OUT8
VDD5:8
OUT9-OUT12
VDD9:12
VDD13:14
OE (see note)
OUT13-OUT14
GND
OUT21-OUT24
VDD21:24
OUT25-OUT27
OUT28/S0
OUT29/S1
OUT30/S2
OUT31/S3
OUT32/S4
Pin Descriptions for 56 pin SSOP (F package)
Type: I = Input, O = output, P = power supply connection, I/O=input upon power up, becoming an output
clock within 10 ms later.
Important Note for OE functionality:
To use the output enable function, once the OE has been taken
low, and the outputs have been tri-stated, the VDD must be removed and reapplied for the clocks to run
again.
Staggered output skews for 56 pin SSOP (F)
To aid in the reduction of EMI, and to allow the board
designer the flexibility of running different length traces whose clock edges will still line up at their
destinations, the MK74ZD133F comes with different fixed skews for different outputs. All skews are with
respect to OUT1 (pin 1), and are measured into 33
termination resistors with 15 pF capacitive loads.
Output Name
OUT2, OUT25:32
OUT4, OUT18:24
OUT3, OUT5:8, OUT13:17
OUT9:12
Pin Numbers
2, 46:49, 52:54, 56
9, 33, 37, 38, 40, 41, 43, 44
8, 11, 12, 14, 15, 25, 26, 30:32
17, 18, 20, 21
Typical Skew
0
- 350 ps
-225 ps
-150 ps
Maximum variation
200 ps
200 ps
200 ps
200 ps
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