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參數(shù)資料
| 型號(hào)： | MK74ZD133Y |
| 英文描述： | PLL and 32-Output Clock Driver |
| 中文描述： | PLL和32個(gè)輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MK74ZD133Y |
MK74ZD133
PLL and 32-Output Clock Driver
PRELIMINARY INFORMAT ION
MDS 74ZD133 C
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
5
Revision 010899
Printed 11/17/00
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input (F)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 26.5
3 - 10
4 - 13.33
5 - 16
reserved
10 - 40
6 - 20
20 - 80
Input (Y)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 44.44
3 - 16.67
4 - 22.22
5 - 26.67
reserved
10 - 66.67
6 - 33.33
20 - 100
Output
90*
30
81*
25
54
50
33.33
27
64
75
83.33*
66.66
133.33*
62.5
31.25
125*
55
53.125
135*
106.25*
106*
106.25*
106.66*
107*
x3
x8
x6
x5
reserved
x2
x4
x1
Output Frequency Select Table
The MK74ZD133 has two primary
modes of operation: “Clock Generator”
and “Zero Delay Multiplier”.
In Clock Generator mode, addresses 0
through 23, specific output frequencies
are generated from a 20 MHz input.
There is no fixed phase relationship
between the input and output clocks.
In Zero Delay Multiplier mode,
addresses 24 through 31, the output
frequency is a simple integer multiple of
the input. The input range can vary over
several MHz, making it possible to
generate output frequencies that are not
included in Clock Generator mode. In
this mode, FBOUT3 is fed back to the
FBIN pin, and the rising edges of the
input and outputs are synchronized.
Configuring the Input/Output
Pins
The MK74ZD133 uses I/O pins whose
status as select inputs are sampled upon
power-up. The chip then selects this
address in the table to the left, and stays
in that configuration until a new power-
up sequence, when the select inputs are
sampled again. These pins all have
internal pull-up resistors, so the 10k
resistor is only needed to connect to
ground for the 0 selection in the table
(as shown below).
Output Frequency Generation
to load
I/O
For select
= 0 (low)
10k
33
Don’t stuff 10k
for“1” selection
* These modes only guaranteed in the Y (LQFP) package
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