參數(shù)資料
型號(hào)： ML6440
廠商： Fairchild Semiconductor Corporation
英文描述： Multi-Standard 8-bit Adaptive Digital Input Comb Filter(多標(biāo)準(zhǔn)8位自適應(yīng)數(shù)字輸入組合濾波器)
中文描述： 多標(biāo)準(zhǔn)的8位數(shù)字輸入自適應(yīng)梳狀濾波器（多標(biāo)準(zhǔn)8位自適應(yīng)數(shù)字輸入組合濾波器）
文件頁(yè)數(shù)： 3/18頁(yè)
文件大?。?/td> 227K
代理商： ML6440
ML6440
3
PIN
NAME
FUNCTION
1
C2
Chrominance output
2
C1
Chrominance output
3
C0
Chrominance output
4
GND
Digital ground pin
5
V
CC
Digital supply pin
6
RST
Reset input active low. Resets comb
logic including the internal data
register. Required at power up.
7
CLK
TTL compatible clock reference
8
CI0/DI0
(LSB) Input Chrominance signal (PAL/
NTSC control pin in control pin mode:
register bit D0)
9
CI1/DI1
Input Chrominance signal (Square
Pixel/CCIR control pin in control pin
mode: register bit D1)
10
CI2/DI2
Input Chrominance signal. (Comb
mode 0 control pin in control pin
mode: register bit D2)
11
CI3/DI3
Input Chrominance signal (Comb
mode 1 control pin in control pin
mode: register bit D3)
12
CI4/DI4
Input Chrominance signal (Adaption
Threshold 0 control pin in control pin
mode: register bit D4)
13
CI5/DI5
Input Chrominance signal (Adaption
Threshold 1 control pin mode: register
bit D5)
14
CI6/DI6
Input Chrominance signal (Adaption
Threshold 2 control pin mode: register
bit D6)
15
CI7/DI7
(MSB) Input Chrominance
(Y+C/YI control pin in control pin
mode: register bit D7)
16
AV
CC
Analog supply pin. Bypass to ground
with 1μF ceramic capacitor
17
GND
Ground pin for analog delay line
18
YI0/CV0
TTL compatible (LSB) Input composite
video signal or Y in the Y+C bypass
mode
19
YI1/CV1
Luma or composite video input signal
PIN DESCRIPTION
PIN
NAME
FUNCTION
20
YI2/CV2
Luma or composite video input signal
21
YI3/CV3
Luma or composite video input signal
22
YI4/CV4
Luma or composite video input signal
23
YI5/CV5
Luma or composite video input signal
24
YI6/CV6
Luma or composite video input signal
25
YI7/CV7
Luma or composite video (MSB) input
signal
26
S
/P
Serial/Parallel program mode. If high,
allows 8-bit parallel control using the
eight digital chrominance input pins.
Data clocks in on the positive edge
transition. If low, serial port active.
27
OE
Output enable. (Y[7:0] and C[7:0]) If
low, outputs high impedance.
28
S DATA
Serial data input
29
S CLK
Serial clock input. Positive-edge
clocks.
30
Y7
TTL compatible luminance output
(MSB)
31
Y6
Luminance output
32
Y5
Luminance output
33
Y4
Luminance output
34
Y3
Luminance output
35
Y2
Luminance output
36
Y1
Luminance output
37
Y0
Luminance output (LSB)
38
GND
Digital ground pin
39
V
CC
Digital supply pin
40
C7
TTL compatible chrominance output
(LSB)
41
C6
Chrominance output
42
C5
Chrominance output
43
C4
Chrominance output
44
C3
Chrominance output
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參數(shù)描述
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