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參數(shù)資料
| 型號(hào)： | ML6440 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multi-Standard 8-bit Adaptive Digital Input Comb Filter(多標(biāo)準(zhǔn)8位自適應(yīng)數(shù)字輸入組合濾波器) |
| 中文描述： | 多標(biāo)準(zhǔn)的8位數(shù)字輸入自適應(yīng)梳狀濾波器（多標(biāo)準(zhǔn)8位自適應(yīng)數(shù)字輸入組合濾波器） |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大小： | 227K |
| 代理商： | ML6440 |
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ML6440
9
Figure 4. Typical Serial Bus Command
Figure 2. Definition of START & STOP on Serial Data Bus
Figure 3. Definition of DATA FORMAT on Serial Data Bus
S DATA
S CLK
START
STOP
t
RISE
t
FALL
t
SET/START
All Other S DATA Transitions Must Occur While S CLK is Low
START: A Falling Edge on the S DATA While S CLK is Held High
STOP: A Rising Edge on the S DATA While S CLK is Held High
S DATA
STOP
MSB
MSB
A1
A0
A6
A7
0
1
2
7
8
9
10
11
16
17
18
D7
D6
D1
D0
S CLK:
S CLK:
S DATA:
S CLK:
S CLK:
S DATA:
S CLK:
S DATA:
9th pulse strobes address decoder
Rising edge enables data transfer
Value set to A6, Device Address (MSB-1)
Falling edge disables data transfer
Rising edge enables data transfer
Value set to A7, Device Address MSB
Falling edge in prep for first address transfer
Falling edge w/S CLK high means start of sequence
S DATA:
S DATA:
S CLK:
S CLK:
S DATA:
S CLK:
S CLK:
S DATA:
Rising edge with S CLK Hi = STOP
Value set low in prep for STOP
18th pulse strobes data shift register
Rising edge enables data transfer
Value set to D6, Data MSB-1
Falling edge disables data transfer
Rising edge enables data transfer
Value set to D7, Data MSB
S CLK
S DATA
S CLK
‘1’
‘0’
‘0’
‘1’
D7
D6
D5
D4
D3
D2
D1
D0
‘0’
‘1’
‘1’
‘1’
0
1
2
3
4
5
9
A
B
C
D
E
F
G
H
I
S CLK:
S DATA:
S CLK:
Address decode strobed on 9th clock
[Data is ‘don’t care’ during strobe]
‘1011 0011’ shifted on next 8 clocks
Falling edge in prep for device address transfer
S
DATA
:
Control register, load MSB first
Final Clock strobes data into register
DEVICE ADDR = ‘B3’
CONTROL REGISTER
STROBE (ACK)
6
8
7
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