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參數(shù)資料
| 型號： | ML6440 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multi-Standard 8-bit Adaptive Digital Input Comb Filter(多標準8位自適應數(shù)字輸入組合濾波器) |
| 中文描述： | 多標準的8位數(shù)字輸入自適應梳狀濾波器（多標準8位自適應數(shù)字輸入組合濾波器） |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 227K |
| 代理商： | ML6440 |
ML6440
6
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL BUS LOGIC INPUT
Low Level Input Voltage
0
0.8
V
High Level Input Voltage
V
CC
– 0.8
V
CC
V
Low Level Input Current
V
IN
= 0V
1.0
μA
High Level Input Current
V
IN
= V
CC
D
1.0
μA
Input Impedance
f
CLK
= 100kHz
1
M
W
Input Capacitance (C
IN
)
2
pF
SYSTEM TIMING
S
CLK
Frequency (f
CLOCK
)
100
kHz
Input Hysteresis (V
HYS
)
0.2
V
Spike Suppression (t
SPIKE
)
Max length for zero response
50
ns
Power Setup Time to Valid Data Inputs
VCC Settled to Within 1%
10
ms
Wait Time From STOP to START
On S
DATA
(t
WAIT
)
1.3
μs
Hold Time for START On S
DATA
(t
HD/START
)
0.6
μs
Setup Time for START On S
DATA
(t
SU/START
)
0.6
μs
Min LOW Time On S
CLK
(t
LOW
)
1.3
μs
Min HIGH Time On S
CLK
(t
HI
)
0.6
μs
Hold Time On S
DATA
(t
HD/DATA
)
5.0
μs
Setup Time On (t
SU/DATA
)
Fast mode (Note 4)
100
ns
Slow mode (Note 4)
250
ns
Rise Time for S
CLK
& S
DATA
(t
LH
)
30
300
ns
Fall Time for S
CLK
& S
DATA
(t
HL
)
30
300
ns
Setup Time for STOP On S
DATA
(t
SU/STOP
)
0.6
μs
Note 1:
Note 2:
Note 3:
Note 4:
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Supply voltage fed through 7.5
W
resistor to all V
CC
pins.
No bandlimiting is performed on the signal bandwidth when the comb is in the “on” state.
Parameter is luma dependent
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