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參數(shù)資料
| 型號： | ML6460 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | CCIR656 NTSC Video Encoder(CCIR656標(biāo)準(zhǔn)NTSC視頻編碼器) |
| 中文描述： | CCIR656 NTSC視頻編碼器（CCIR656標(biāo)準(zhǔn)NTSC制式視頻編碼器） |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 217K |
| 代理商： | ML6460 |
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ML6460
10
REV. 1.0 10/25/2000
FIELD (1,2 and 3,4)
FIELD (ODD/EVEN)
H
L
H
L
ANALOG FIELDS 1 & 2
ANALOG FIELDS 3 & 4
ANALOG FIELDS 1 & 2
ODD
EVEN
ODD
EVEN
ODD
EVEN
Figure 2a. FIELD Pin Output Summary
active edge of HSYNC
HSYNC
VSYNC
coincident interval
for HRESET_MODE=0
64 pixels
–32 pixels
active edge of HSYNC
HSYNC
VSYNC
coincident interval
for HRESET_MODE=1
64 pixels
active edge of VSYNC
active edge of VSYNC
Figure 3. Coincident Valid Sync Intervals for External Slave Mode
PIXEL SYNCHRONIZATION
Master Mode
In this mode, the active edge of horizontal sync pulse
through the HSYNC pin (configured as an output)
indicates the beginning of an active video line (or the
beginning of the horizontal blanking) and the
multiplexed YCrCb pixel data must be synchronized to
this edge for proper video location, as well as the proper
demultiplexing of YCrCb values. This synchronization, as
shown in Figures 4 through 5a, is controlled by
SEL_HSYNC1 (B14) and SEL_HSYNC0 (B13). Figures 4
and 4a show synchronization for active edge at the
beginning of active video for positive or negative HSYNC
polarity while Figures 5 and 5a show synchronization for
active edge at the beginning of horizontal blanking for
positive or negative HSYNC polarity.
FUNCTIONAL DESCRIPTION
(Continued)
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