參數(shù)資料
型號： ML6460
廠商： Fairchild Semiconductor Corporation
英文描述： CCIR656 NTSC Video Encoder(CCIR656標準NTSC視頻編碼器)
中文描述： CCIR656 NTSC視頻編碼器（CCIR656標準NTSC制式視頻編碼器）
文件頁數(shù)： 13/30頁
文件大?。?/td> 217K
代理商： ML6460
ML6460
REV. 1.0 10/25/2000
13
Internal Slave Mode
Embedded in the YCrCb data stream, the timing code
0xFF, 0x00, 0x00, 0x(SAV) must be inserted before the
samples of the first active pixel. Figures 6 through 6b
illustrate timing for CCIR656 video with SAV and EAV
codes for CCIR or Square Pixel clocking.
External Slave Mode
A horizontal reset pulse can be used either at the beginning
of active video or the beginning of horizontal blanking to
provide synchronization of the YCrCb data to the internal
clock. Bits SEL_HSYNC1(B14) and SEL_HSYNC0 (B13) are
provided to achieve some degree of programmability in this
synchronization. Figures 7 and 7a show synchronization for
active edge at the beginning of active video for positive or
negative HSYNC polarity while Figures 8 and 8a show
synchronization for active edge at the beginning of
horizontal blanking for positive or negative HSYNC polarity.
Polarity of HSYNC and VSYNC
In both the Master and Slave modes, the HSYNC and
VSYNC polarity can be selected via bit SENSE_HSYNC
and SENSE_VSYNC. When the SENSE_HSYNC bit is set to
logical 1, the HSYNC pulse is on the rising edge. When the
SENSE_HSYNC bit is cleared to logical 0, the HSYNC pulse
is on the falling edge. Similarly, when the SENSE_VSYNC
bit is set logical 1, the VSYNC pulse is on the rising edge.
Figure 6. CCIR Format: CLK = 27MHz
FUNCTIONAL DESCRIPTION
(Continued)
When the SENSE_VSYNC bit is cleared to logical 0, the
VSYNC pulse is on the falling edge.
HSYNC Timing Delay
In both Master and Slave modes, the SEL_HSYNC1(B14)
and SEL_HSYNC0 (B13) bits of the control register can be
programmed to delay the HSYNC active edge up to three
clock periods, 3T, where T is one period of the clock.
CHROMA AND LUMA PROCESSING
Refer to Figures 9 through 12.
VIDEO OUTPUT STAGE
Reconstruction filtering, clamping, and line drivers
The ML6460 can simultaneously provide outputs for S-
video, two composite video, and a TV modulator.
Differential gain and phase are guaranteed at the outputs
of the line drivers. Two internal 7
th
-order Butterworth
filters and a group delay equalizer are used as
reconstruction filters on S-video (NTSC). The composite
signal is generated after reconstruction. The S-video (Y
and C) and composite video (CV) are then fed into 75
line drivers.
Each of the filter/drivers are designed to guarantee a
differential phase of 0.5o and differential gain of 0.5%.
F
F
CB0
Y0
CR0
Y1
CB1
Y2
CR1
Y3
CB2
Y4
0
0
0
0
E
A
V
8
0
1
0
8
0
1
0
8
0
1
0
F
F
0
0
0
0
S
A
V
C
B
Y C
R
Y C
B
Y C
R
Y
Y C
B
Y C
R
Y
Y715
CB358
Y716
CR358
Y717
CB359
Y718
CR359
Y719
0 1 2 3 4 5 6 7
270
272
274
276
278
280
282
171117131715
1440
1440
4
4
268
In CCIR format, there are
{ }
in the active portion of a line.
720 Y
360 Cb
360 Cr
ACTIVE
BLANKING
ACTIVE
LINE
LINE
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