DYNAMIC ELECTRICAL CHARACTERISTICS DYNAM" />
參數(shù)資料
型號: MM908E624ACDWBR2
廠商: Freescale Semiconductor
文件頁數(shù): 3/39頁
文件大?。?/td> 0K
描述: IC TRPL SWITCH MCU/LIN 54-SOIC
標(biāo)準(zhǔn)包裝: 1,000
應(yīng)用: 自動鏡像控制
核心處理器: HC08
程序存儲器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 16
電源電壓: 5.5 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
供應(yīng)商設(shè)備封裝: 54-SOIC
配用: KIT908E624DWBEVB-ND - KIT EVAL 908E624 TRPL W/MCU/LIN
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
908E624
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 °C TJ 125 °C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate (19), (20)
Dominant Propagation Delay TXD to LIN
tDOM-MIN
——
50
μs
Dominant Propagation Delay TXD to LIN
tDOM-MAX
——
50
μs
Recessive Propagation Delay TXD to LIN
tREC-MIN
——
50
μs
Recessive Propagation Delay TXD to LIN
tREC-MAX
——
50
μs
Propagation Delay Symmetry: tDOM-MIN - tREC-MAX
DT1
-10.44
μs
Propagation Delay Symmetry: tDOM-MAX - tREC-MIN
DT2
11
μs
Driver Characteristics for Slow Slew Rate (19), (21)
Dominant Propagation Delay TXD to LIN
tDOM-MIN
100
μs
Dominant Propagation Delay TXD to LIN
tDOM-MAX
100
μs
Recessive Propagation Delay TXD to LIN
tREC-MIN
100
μs
Recessive Propagation Delay TXD to LIN
tREC-MAX
100
μs
Propagation Delay Symmetry: tDOM-MIN - tREC-MAX
DT1S
-22
μs
Propagation Delay Symmetry: tDOM-MAX - tREC-MIN
DT2S
23
μs
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SRFAST
—15
V/
μs
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay (22)
tRL
—3.5
6.0
μs
Receiver Recessive Propagation Delay (22)
tRH
—3.5
6.0
μs
Receiver Propagation Delay Symmetry
tR-SYM
-2.0
2.0
μs
Bus Wake-up Deglitcher
tPROPWL
35
150
μs
Bus Wake-up Event Reported (23)
tWAKE
—20
μs
Notes
19.
VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
20.
21.
22.
Measured between LIN signal threshold VIL or VIH and 50% of RXD signal.
23.
tWAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 15. In Sleep mode the VDD
rise time is strongly dependent upon the decoupling capacitor at VDD pin.
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