參數(shù)資料
型號(hào)： MPC106ARX83DE
廠商： MOTOROLA INC
元件分類： 總線控制器
英文描述： PCI Bridge/Memory Controller
中文描述： PCI BUS CONTROLLER, CBGA304
封裝： 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-304
文件頁數(shù)： 23/28頁
文件大?。?/td> 158K
代理商： MPC106ARX83DE
MPC106 PCI Bridge/Memory Controller Hardware Specifications
23
System Design Information
1.8.2 PLL Power Supply Filtering
The AVdd power signal is provided on the 106 to provide power to the clock generation phase-locked loop.
To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered
using a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to
the AVdd pin to ensure it filters out as much noise as possible.
Figure 13. PLL Power Supply Filter Circuit
1.8.3 Decoupling Recommendations
Due to the 106’s large address and data buses and high operating frequencies, it can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the system, and the 106 itself requires a
clean, tightly regulated source of power.
It is strongly recommended that the system design include six to eight 0.1
μ
F (ceramic) and 10
μ
F
(tantalum) decoupling capacitors to provide both high- and low-frequency filtering. These capacitors
should be placed closely around the perimeter of the 106 package (or on the underside of the PCB). It is
also recommended that these decoupling capacitors receive their power from separate Vdd and GND
power planes in the PCB, utilizing short traces to minimize inductance. Only surface mount technology
(SMT) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd plane, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors—100
μ
F (AVX TPS tantalum) or 330
μ
F (AVX TPS tantalum).
1.8.4 Connection Recommendations
To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level.
Unused active low inputs should be tied (using pull-up resistors) to Vdd. Unused active high inputs should
be tied (using pull-down resistors) to GND. All no-connect (NC) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, AVdd, and GND pins of the 106.
1.8.4.1 Pull-up Resistor Recommendations
The MPC106 requires pull-up (or pull-down) resistors on several control signals of the 60x and PCI buses
to maintain the control signals in the negated state after they have been actively negated and released by the
106 or other bus masters. The JTAG test reset signal, TRST, should be pulled down during normal system
operation. Also, as indicated in Table 10, the factory test signal, LSSD_MODE, must be pulled up for
normal device operation
During inactive periods on the bus, the address and transfer attributes on the bus (A[0–31], TT[0–4],
TBST, WT, CI, and GBL) are not driven by any master and may float in the high-impedance state for
relatively long periods of time. Since the MPC106 must continually monitor these signals, this float
Vdd
(3.3 V)
AVdd
10
10 μF
0
.
1 μF
GND
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