25-30
MPC561/MPC563 Reference Manual
MOTOROLA
IEEE 1149.1 Test Access Port
5. The PORESET, HRESET, and SRESET pins are not part of the JTAG boundary scan chain. These pins are used in
the reset configuration to enter JTAG. Board-level connections to them will not be testable with the EXTEST and
CLAMP instructions. They do respond to the HI-Z JTAG instruction for parametric testing purposes.6.
6. The XTAL, EXTAL, and XFC pins are associated with analog signals and are excluded from the boundary scan chain.
7. The READI module reset pin, rsti_b, (bsdl pin 517) is in the JTAG boundary scan chain, but must be kept at a “0” level
during JTAG testing, (except for Hi-Z testing), due to system interactions. It is classified as a “l(fā)inkage” pin, and its data
and control cells are configured to advise ATPG tools to drive a “0” value in during JTAG testing.
8. Pad type naming conventions:
26 V – 2.6 V
5 V – 5 V
s – slow
f – fast
h – high drive
a – analog input
i – input only
d – has direct connection to the pad (may be used for module test)
r – resized cell instance
9. Column Descriptions:
Columns 1 through 8 are entries from the boundary-scan description from the BSDL file. The columns and formats
for each of these entries are defined in the IEEE Std. 1149.1b-1994 Supplement to the IEEE Std. 1149.1-1990, IEEE
Standard Test Access Port and Boundary-Scan Architecture document. Descriptions of these columns are
described below:
Column 1: Defines the bit’s ordinal position in the boundary scan register. The shift register cell nearest TDO (i.e.,
first to be shifted in) is defined as bit 0; the last bit to be shifted in is 519.
Column 2: References one of the three standard JTAG Cell Types (BC_4, BC_2, and BC_7) that are used for this
JTAG cell in the MPC561/MPC563. See the IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and
Boundary-Scan Architecture document for further description of these standard cell types.
Column 3: Lists the pin name (also called the PortID) for all pin-related cells. For JTAG control cells or data cells
that have been designated as “internal”, an asterisk, is shown in this column.
Column 4: Lists the BSDL pin function.
Column 5: The “safe bit” column specifies the value that should be loaded into the capture (and update) flip-flop of
a given cell when board-level test generation software might otherwise choose a value randomly.
Column 6: The “control cell” column identifies the cell number of the control cell that is associated with this data
cell, and can disable its output.
Column 7: The “disable value” column gives the value that must be scanned into the control cell identified by the
previous “control cell” (column 6) to disable the port named by the relevant portID.
Column 8: The “disable result” column identifies a given signal value of the PortID if that signal can be disabled.
The values shown specifies the condition of the driver of that signal when it is disabled.
Column 9: The “pin function” column indicates the normal system pin directionality. (– Input Only Pin, O – Output
Only Pin, I/O – Bidirectional I/O pin)
Column 10: The pad type column describes relevant characteristics about each pad type. See the Pad Type Keys
in Note 5 above.
25.1.3
Instruction Register
The MPC561/MPC563 JTAG implementation includes the public instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS), and also supports the CLAMP instruction. One
additional public instruction (HI-Z) provides the capability for disabling all device output
drivers. The MPC561/MPC563 includes a 4-bit instruction register without parity
consisting of a shift register with four parallel outputs. Data is transferred from the shift
register to the parallel outputs during the update-IR controller state. The four bits are used
to decode the five unique instructions listed in.