MOTOROLA
Index
Index-13
condition register (CR),
3-17conversion command word table (CCW),
13-31,count register (CTR),
3-21CRAM_RBAx CALRAM region base address
CRAMMCR CALRAM module configuration
CRAMOVL CALRAM overlay configuration
DAE/source instruction service register (DSISR),
data address register (DAR),
3-24DCCR0-DCCR15 decompressor class
configuration registers,
A-21debug enable register (DER),
23-46decompressor class configuration,
4-26decrementer register (DEC),
6-42development port data register (DER),
23-57documenter register (DEC),
3-24DPTRAM base address register (RAMBAR),
20-5DPTRAM module configuration register
DPTRAM test register (DPTTCR),
20-5dual-mapping base register (DMBR),
10-37dual-mapping option register (DMOR),
10-38EIBADR external interrupt relocation table base
exception cause register (ECR),
23-45external master control register (EMCR),
6-31floating point (FPRs),
3-14floating point exception cause register (FPECR),
floating point status and control register (FPSCR),
general purpose registers (GPRs),
3-13hard reset configuration word register (UC3FCFIG),
I-bus support control register (COUNTA),
23-54I-bus support control register (ICTRL),
A-18implementation specific SPRs,
3-27integer exception register (XER),
3-19internal memory map register (IMMR),
6-30interrupt in-service registers (SISR2 and SISR3),
IRAMSTBY control register (VSRMCR),
8-39L2U global region attribute registers (L2U_GRA),
L2U module configuration register (L2U_MCR),
L2U region attribute registers (L2U_RAx),
11-16L2U region base address registers (L2U_RBAx),
L-bus support control register 1 (LCTRL1),
23-51L-bus support control register 2 (LCTRL2),
23-52left justified, unsigned result format (LJURR),
machine state (MSR),
3-21machine status save/restore register 0 (SRR0),
3-25machine status save/restore register 1 (SRR1),
3-25MBISM interrupt registers,
17-71MBISM registers, list of,
17-13MCPSMSCR MCPSM status/control register,
17-18MDASM status/control register (duplicated)
MDASM status/control register (MDASMSCR),
MDASMAR MDASM Data A register,
17-42MDASMBR MDASM Data B register,
17-43memory controller base registers (BR0-BR3),
10-33memory controller option registers (OR0-OR3),
memory controller status registers (MSTAT),
10-33MI_GRA global region atribute register,
4-24MI_RA [0:3] region attribute register,
4-23MI_RBA[0:3] region base address register,
4-22MIOS14ER0 interrupt enable register,
17-67MIOS14ER1 interrupt enable register,
17-69MIOS14LVL0 interrupt level register 0,
17-71MIOS14LVL1 interrupt level register 1,
17-71MIOS14MCR module configuration register,
17-15MIOS14RPR0 interrupt request pending register 0,
MIOS14RPR1 interrupt request pending register 1,
MIOS14SR0 interrupt status register,
17-67MIOS14SR1 interrupt status register,
17-69MIOS14TPCR test and signal control register,
MIOS14TVECT vector register,
17-14MIOS14VNR module and version number register,
MISC counter register (MISCNT),
20-6MMCSMCNT MMCSM up-counter register,
17-24MMCSMML MMCSM modulus latch register,
MMCSMSCR MMCSM status/control register,