MOTOROLA
Chapter 23. Development Support
23-33
Development Port
23.4.5.3 VFLS[0:1]/MPIO32B[3:4] Signals
The VFLS[0:1]/MPIO32B[3:4] signals power up as the MPIO32B[3:4] function and their
function can be changed via the VFLS bit in the MIOS14TPCR register. The FRZ state is
indicated by the value 0b11 on the VFLS[0:1] signals.
23.4.6
Development Port Registers
The development port consists logically of the three registers: development port instruction
register (DPIR), development port data register (DPDR), and trap enable control register
(TECR). These registers are physically implemented as two registers, development port
shift register and trap enable control register. The development port shift register acts as
both the DPIR and DPDR depending on the operation being performed. It is also used as a
temporary holding register for data to be stored into the TECR. These registers are
discussed below in more detail.
23.4.6.1 Development Port Shift Register
The development port shift register is a 35-bit shift register. Instructions and data are shifted
into it serially from DSDI using DSCK (or CLKOUT depending on the debug port clock
Mode Selection”) as the shift clock. These instructions or data are then transferred in parallel to the CPU, the trap enable control register (TECR). When the processor enters
debug mode it fetches instructions from the DPIR which causes an access to the
development port shift register. These instructions are serially loaded into the shift register
from DSDI using DSCK (or CLKOUT) as the shift clock. In a similar way, data is
transferred to the CPU by moving it into the shift register which the processor reads as the
result of executing a “move from special purpose register DPDR” instruction. Data is also
parallel-loaded into the development port shift register from the CPU by executing a “move
to special purpose register DPDR” instruction. It is then shifted out serially to DSDO using
DSCK (or CLKOUT) as the shift clock.
23.4.6.2 Trap Enable Control Register
The trap enable control register is a 9-bit register that is loaded from the development port
shift register. The contents of the control register are used to drive the six trap enable
signals, the two breakpoint signals, and the VSYNC signal to the CPU. The “transfer data
to trap enable control register” commands will cause the appropriate bits to be transferred
to the control register.
The trap enable control register is not accessed by the CPU, but instead supplies signals to
the CPU. The trap enable bits, VSYNC bit, and the breakpoint bits of this register are
loaded from the development port shift register as the result of trap enable mode
transmissions. The trap enable bits are reflected in ICTRL and LCTRL2 special registers.