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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-123
SERIAL
I/F
COMMUNICATION
16
PROCESSOR
MODULE
LST—Last Entry in the RAM
Whenever the serial interface RAM is used, this bit must be set in one of the TX or RX entries
of each group. Even if all entries of a group are used, this bit must still be set in the last entry.
0 = This is not the last entry in this section of the route RAM.
1 = This is the last entry in this RAM. After this entry, the serial interface waits for the
sync signal to start the next frame.
16.7.4.4 SERIAL INTERFACE RAM DYNAMIC CHANGES. The serial interface RAM has
two operating modes:
A time-division mulitplex channel with a static routing definition. The serial interface
RAM is divided into two parts (RX and TX).
A time-division mulitplex channel that allows dynamic changes. The serial interface
RAM is divided into four parts.
Dynamic changes allow the routing definition of a TDMA to be modified while the serial
communication controller and serial management controllers are connected to it. With fixed
routing, a change has three requirements that must be met before the new routing takes
effect:
The serial communication controller and serial management controllers connected to
the time-slot assigner must be disabled.
The serial interface routing must be modified.
The serial communication controller and serial management controllers connected to
the time-slot assigner must be reenabled.
Dynamic changes divide portions of the serial interface RAM into current-route and shadow
RAM. Once the current-route RAM is programmed, the time-slot assigner and serial
interface channels are enabled and time-slot assigner operation begins. When you need to
make a change in routing, you must program the shadow RAM with the new route and set
the CSRRA bit in the SIMCR to receive and the CSRTA bit to transmit. As a result, the serial
interface exchanges the shadow RAM and the current-route RAM as soon as the
corresponding sync arrives and resets the appropriate CSRxA bit to signify that the
operation has completed. At this time, you can change the routing again. Notice that the
original current-route RAM is now the shadow RAM and vice versa.
Figure 16-49 illustrates
an example of the shadow RAM exchange process.
Note: If a second sync signal is received before the end of a frame (as defined by the
last serial interface RAM entry), an error occurs. The serial interface will
terminate RAM processing and cease transmitting or receiving data until a third
sync signal is received.