
Development Capabilities and Interface
20-26
MPC823 USER’S MANUAL
MOTOROLA
DEVELOPMENT
20
CAPABILITIES
&
INTERFACE
To avoid entering debug mode after reset, the DSCK pin must be negated no later than
seven clock cycles after SRESET negates to allow the processor to jump to the reset vector
and begin normal execution. Entering debug mode immediately after reset, Bit 31
(development port interrupt bit) of ICR is set. For details, refer to the timing diagram
When debug mode is disabled, all events result in regular interrupt handling. The internal
freeze signal is asserted whenever an enabled event occurs, regardless of whether or not
debug mode is enabled or disabled. The internal freeze signal is connected to all relevant
internal modules. These modules can be programmed to stop all operations in response to
Indication (FRZ). Furthermore, the freeze indication is negated when exiting the debug
The following list of events can cause the core to enter debug mode. Each event results in
debug mode entry if debug mode is enabled and the corresponding enable bit is set. The
reset values of the enable bits allow debug mode features to be used even when debug
System reset as a result of SRESET assertion
Checkstop
Machine check interrupt
Implementation specific instruction TLB miss
Implementation specific instruction TLB error
Implementation specific data TLB miss
Implementation specific data TLB error
External interrupt, recognized when MSREE =1
Alignment interrupt
Program interrupt
Floating-point unavailable interrupt
Decrementer interrupt, recognized when MSREE =1
System call interrupt
Trace asserted when in single or branch trace mode
Implementation dependent software emulation interrupt
Instruction breakpoint is recognized only when MSRRI =1 and when breakpoints are
masked. When breakpoints are not masked, they are always recognized.
Load/store breakpoint is recognized only when MSRRI = 1 and when breakpoints are
masked. When breakpoints are not masked, they are always recognized.