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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-129
SERIAL
I/F
COMMUNICATION
16
PROCESSOR
MODULE
DSCA—Double Speed Clock for TDMA
This bit controls how some time-division multiplex channels, such as GCI, define the input
clock to be two times faster than the data rate.
0 = The channel clock (L1RCLKA and/or L1TCLKA) is equal to the data clock. Use for
IDL and most TDM formats.
1 = The channel clock rate is twice the data rate. Use for GCI.
CRTA—Common Receive and Transmit Pins for TDMA
This bit is useful when the transmit and receive sections of a given TDMA use the same
clock and sync signals. In this mode, the L1TCLKA and L1TSYNCA pins can be used as
general-purpose I/O pins.
0 = Separate pins. The receive section of this TDMA uses L1RCLKA and L1RSYNCA
pins for framing and the transmit section uses L1TCLKA and L1TSYNCA for
framing.
1 = Common pins. The receive and transmit sections of this TDMA use L1RCLKA as
clock pin of the channel and L1RSYNCA as the receive and transmit sync pin. Use
for IDL and GCI.
STZA—Set L1TXDA to Zero for TDMA
0 = Normal operation.
1 = L1TXDA is set to zero until serial clocks are available, which is useful for GCI
activation.
CEA—Clock Edge for TDMA
0 = Data is transmitted on the rising edge of the clock and received on the falling edge
(use for IDL and GCI).
1 = Data is transmitted on the falling edge of the clock and received on the rising edge.
FEA—Frame Sync Edge for TDMA
This bit indicates when the L1RSYNCA and L1TSYNCA pulses are sampled with the falling
or rising edge of the channel clock.
0 = Falling edge. Use for IDL and GCI.
1 = Rising edge.
GMA—Grant Mode for TDMA
0 = GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is
internally supported. The grant is one bit from the receive channel. This bit is
marked by programming the channel select bits of the serial interface RAM with
1 = IDL mode. A grant mechanism is supported if the corresponding GR2 bit in the
SICR register is set. The grant is a sample of the L1GRA pin while L1TSYNCA is
asserted. This grant mechanism implies the IDL access controls for transmission
on the D channel.