Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-263
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
If the CM bit in the TX buffer descriptor is set, the SCC2 ASYNC HDLC controller writes the
signal unit status bits into the buffer descriptor after transmission but it does not clear the R
bit. The SCC2 ASYNC HDLC controller then proceeds to the next TX buffer descriptor in the
table. If it is not ready, it waits until it is ready. While the SCC2 ASYNC HDLC controller is
transmitting data from the buffers, it automatically performs the transparency encoding
You should issue the STOP TRANSMIT command to rearrange the transmit queue before
the communication processor module finishes transmitting all the buffers. This can be useful
when transmitting expedited data prior to previously linked buffers or for error situations.
When the SCC2 ASYNC HDLC controller receives the STOP TRANSMIT command, it stops
transmitting and sends the abort sequence. It then transmits idle characters until the
RESTART TRANSMIT command is given, at which point it resumes transmission with the
next TX buffer descriptor.
16.9.19.3 SCC2 ASYNC HDLC CHANNEL FRAME RECEPTION PROCESS. The SCC2
ASYNC HDLC receiver is designed to work with a minimum amount of intervention from the
core and can decode the transparency characters, check the CRC of the frame, and detect
errors on the line and in the controller. When the core enables the receiver, the receiver
waits for data to be present on the line. When the receiver detects a data byte of the
incoming frame that was preceded by one or more opening flags, the SCC2 ASYNC HDLC
controller fetches the next buffer descriptor and if the E bit is set it starts transferring the
incoming frame into the buffer descriptor associated data buffer. When the data buffer is full,
the SCC2 ASYNC HDLC controller clears the E bit in the buffer descriptor. If the incoming
frame exceeds the length of the data buffer, the SCC2 ASYNC HDLC controller fetches the
next buffer descriptor in the table and, if empty, continues transferring the rest of the frame
into the associated data buffer.
During this process, the receiver automatically decodes the transparency character required
of the SCC2 ASYNC HDLC protocol. This procedure is described in detail in
controller checks the incoming CRC field and writes it to the data buffer. It then writes the
length of the entire frame to the DATA LENGTH field of the last buffer descriptor. The SCC2
ASYNC HDLC controller sets the L bit, writes the frame status bits into the buffer descriptor,
and clears the E bit if the CM bit is clear. It then sets the RXF bit in the SCCE–ASYNC HDLC
register, which indicates that a frame has been received and is in memory. The SCC2
ASYNC HDLC controller then waits for the start of the next frame which may or may not have
an opening flag.
Figure 16-89. ASYNC HDLC Frame Structure
BOF
EOF
FCS
I
C
A
8 BITS
2 * 8 BITS
M * 8 BITS