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Communication Processor Module
16-356
MPC823 USER’S MANUAL
MOTOROLA
USB
COMMUNICATION
16
PROCESSOR
MODULE
FLG—The bit is set by the core and cleared by the communication processor module.
0 =
The communication processor module is ready to receive a new command.
1 =
The CPCR contains a command that the communication processor module is
currently processing. The communication processor module clears this bit
when the command finishes executing or after reset.
16.10.7 USB Controller Errors
The USB controller reports frame reception and transmission error conditions using the
channel buffer descriptors and the USB event register. The following transmission errors
can be detected by the USB controller.
Transmit Underrun Error—If this error occurs, the channel forces a bit-stuffing violation,
terminates buffer transmission, closes the buffer, sets the UN bit in the TX buffer
descriptor, and sets the corresponding TXE bit in the USB event register. The endpoint
resumes transmission after the RESTART TX ENDPOINT command is received.
Transmit Timeout Error—If this error occurs, the channel tries to retransmit if the RTE
bit is set in the USB endpoint configuration register. If the RTE bit is not set or the
second attempt fails, the channel closes the buffer, sets the TO bit in the TX buffer
descriptor, and sets the corresponding TXEx bit in the USB event register. The endpoint
resumes transmission after the RESTART TX ENDPOINT command is received.
TX Data Not Ready Error—This error occurs if an IN token was received, but the
corresponding endpoint’s FIFO was empty, or if the endpoint was configured to NAK or
STALL. The channel will set the TXEx bit in the USB event register.
The following reception errors can be detected by the USB controller.
Overrun Error—The USB controller maintains an internal FIFO for receiving data. If a
receive overrun occurs, the channel writes the received data byte to the internal FIFO
over the previously received byte. The channel closes the buffer, sets the OV bit in the
buffer descriptor, and sets the RXB bit in the USB event register. The NAK handshake
is transmitted at the end of the received packet if the packet was error-free.
Busy Error—A frame was received and discarded due to a lack of buffers. The channel
sets the BSY bit in the USB event register.
Non Octet Aligned Packet Error—If this error occurs, the channel writes the received
data to the data buffer, closes the buffer, sets the NO bit in the RX buffer descriptor, and
generates a RXB interrupt.
CRC Error—When a CRC error occurs, the channel closes the buffer, and sets the CR
bit in the RX buffer descriptor and the RXB bit in the USB event register. In isochronous
mode, the USB controller reports a CRC error, however, there are no handshake
packets (ACK) and the transfer continues normally when an error occurs.