Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-295
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
If just one of the TTX or TRX bits is set, the other half of the serial communication controller
operates with another protocol as programmed in the MODE field of the GSMR_L. This
allows loopback modes to DMA data from one memory location to another while converting
the data to a specific serial format. The SCC2 in Transparent mode can work with the
time-slot assigner or nonmultiplexed serial interface and support modem lines with the
general-purpose I/O pins. The data can be transmitted and received with the MSB or LSB
first in each octet.
The SCC2 in Transparent mode consists of separate transmit and receive sections whose
operations are asynchronous with the core. Each clock can be supplied from the internal
baud rate generator bank, DPLL output, or external pins.
16.9.21.1 FEATURES. The following list summarizes the main features of the SCC2 in
Transparent mode:
Flexible data buffers
Automatic Sync detection on reception
CRCs can be transmitted and received
Reverse data mode
Another protocol can be performed on the other half of the SCC2 in Transparent mode
16.9.21.2 SCC2 TRANSPARENT CHANNEL FRAME TRANSMISSION PROCESS. The
transparent transmitter is designed to work with almost no intervention from the core and
when the core enables the SCC2 transmitter in transparent mode, it starts transmitting idles.
The serial communication controller polls the first buffer descriptor in the channel’s transmit
(TX) buffer descriptor table. When there is a message to transmit, the serial communication
controller fetches the data from memory, loads the transmit FIFO, and waits for transmitter
synchronization before transmitting the message.
Transmitter synchronization can be achieved with the CTS pin or by waiting for the receiver
to achieve synchronization, depending on how the TXSY bit is set in the GSMR_H. Once
transmitter synchronization is achieved, transmission begins.
When buffer descriptor data has been completely transmitted, the L bit is checked and if it
is set, the serial communication controller writes the message status bits into the buffer
descriptor and clears the R bit. It then starts transmitting idles until the next buffer descriptor
is ready and if it is ready some idles are still transmitted. The transmitter only begins
transmission again after it achieves synchronization. When the end of the current buffer
descriptor has been reached and the L bit is cleared, only the R bit is cleared and the
transmitter moves immediately to the next buffer to begin transmission with no gap on the
serial line between buffers. Failure to provide the next buffer in time results in a transmit
underrun, thus causing the TXE bit in the SCCE–Transparent register to be set.