參數資料
型號： MPC8241LZQ266D
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357
封裝： 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357
文件頁數： 15/64頁
文件大小： 827K
代理商： MPC8241LZQ266D
22
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
11c
PCI_SYNC_IN to inputs invalid (input hold)
1.0
—
ns
1, 2, 3
Notes:
1. All PCI signals are measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × GVDD_OVDD of the
signal in question for 3.3-V PCI signaling levels. See Figure 12.
2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the
signal in question to the VM = 1.4 V of the rising edge of the memory bus clock. sys_logic_clk. sys_logic_clk is the
same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising
edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 11.
3. Input timings are measured at the pin.
4. tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question
to the VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 13.
6. The memory interface input setup and hold times are programmable to four possible combinations by programming
bits 5:4 of register offset <0x77> to select the desired input setup and hold times.
7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay
present on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM
clocks become offset by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN must be shortened to accommodate this range relative to the SDRAM clock output trace lengths
to maintain phase-alignment of the memory clocks with respect to sys_logic_clk. It is recommended that the length
of SDRAM_SYNC_OUT to SDRAM_SYNC_IN be shortened by 0.7 ns. This is because that is the midpoint of the
range of Tos and allows the impact from the range of Tos to be reduced. Additional analyses taking into account trace
lengths and SDRAM loading will need to be performed to optimize timing. For more details on trace measurements
and accommodating for the Tos problem, refer to the Motorola application note AN2164, MPC8245/MPC8241
Memory Clock Design Guidelines.
Table 10. Input AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
相關PDF資料
PDF描述
MPC8241LZP266B 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357
MPC8241LZQ166B 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357
MPC8241LZQ266B 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357
MPC8241LVR200B 32-BIT, 200 MHz, RISC PROCESSOR, PBGA357
MPC8245ARZU400D 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352
相關代理商/技術參數
參數描述
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MPC8241TVR200D 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8241TZP166C 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications
MPC8241TZP200C 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications
MPC8241TZP266C 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications
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