- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45354 > MPC8241LZQ266D (MOTOROLA INC) 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC8241LZQ266D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357 |
| 文件頁數(shù)： | 37/64頁 |
| 文件大?。?/td> | 827K |
| 代理商： | MPC8241LZQ266D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
42
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
PLL Configuration
6
PLL Configuration
The PLL_CFG[0:4] signals configure the internal PLLs of the MPC8241. For a specific PCI_SYNC_IN
(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)
DA[14:15]
B6 D8
Output
GVDD_OVDD
DRV_MEM_CTRL
1, 19
Notes:
1. Multi-pin signals such as AD[31:0] or MDL[0:31] physical package pin numbers are listed in order corresponding to
the signal names. Ex: AD0 is on pin U1, AD1 is on pin U2,..., AD31 is on pin U13.
2. This pin is affected by a programmable PCI_HOLD_DEL parameter.
3. Motorola recommends placing a weak pull-up resistor (2–10 k
) ion this PCI control pin to LVDD.
4. GNT4 is a reset configuration pin with an internal pull-up resistor that is enabled only when the MPC8241 is in the
reset state.
5. This pin is a multiplexed signal and appears more than once in this table.
6. This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not
guaranteed, but is sufficient to prevent unused inputs from floating.
7. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification (Rev. 2.2).
8. This pin is an open drain signal.
9. DL[0] is a reset configuration pin with an internal pull-up resistor that is enabled only when the MPC8241 is in the
reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is
read into configuration bits during reset.
10.This pin has an internal pull-up resistor that is enabled only when the MPC8241 is in the reset state. The value of
the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits
during reset.
11.This pin is a reset configuration pin.
12.Motorola recommends placing a weak pull-up resistor (2–10 k
) on this pin to GVDD_OVDD.
14.External PCI clocking source or fanout buffer may be required for system if using the MPC8241 DUART
functionality because PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART
mode.
15.OSC_IN utilizes the 3.3-V PCI interface driver that is 5-V tolerant. See Table 2 for details.
16.This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open-drain.
17.All grounded pins are connected together. Connections should not be made to individual pins. The list represents
the balls that are connected to Ground.
18.GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset.
Note that GVDD_OVDD pins are all shorted together, PWRRING. The list represents the balls that are connected
to PWRRING. Connections should not be made to individual PWRRING pins.
19.Treat these pins as No Connects unless using debug address functionality.
20.PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation of
HRST_CTRL and HRST_CPU negate in order to be latched.
21.Place a pull-up resistor of 120
or less on the TEST0 pin.
22.SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev. 1.1 (A). These signals
use DRV_MEM_CLK for chip Rev. 1.2B.
23.The driver capability of this pin is hardwired to 40
and cannot be changed.
24.Motorola typically expects that customers using the serial port will have sufficient drivers available in the RS232
transceiver to drive the CTS pin actively as an input if they are using that mode. No pullups would be needed in
these circumstances.
Table 17. MPC8241 Pinout Listing (continued)
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output
Driver Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8241LZP266B | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LZQ166B | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LZQ266B | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LVR200B | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA357 |
| MPC8245ARZU400D | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8241TVR166D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8241TVR200D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8241TZP166C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications |
| MPC8241TZP200C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications |
| MPC8241TZP266C | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Intergrated Processor Hardware Specifications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。