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參數(shù)資料
| 型號： | MPC8241LZQ266D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357 |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 827K |
| 代理商： | MPC8241LZQ266D |
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48
MPC8241 Integrated Processor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
System Design Information
Power and ground connections must be made to all external VDD, GVDD_OVDD, LVDD, and GND pins of
the MPC8241.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8241.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8241. The trace length may be used to skew or adjust
the timing window as needed. See Motorola application notes AN1849/D, the Tundra Tsi107 Design
Guide, and AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines, for more information
about this topic. Note the SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see Table 10).
7.4 Pull-Up/Pull-Down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress, and thus do not
require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31]
and PAR[4:7]) are disabled, and their outputs drive logic zeros when they would otherwise be driven. For
this mode, these pins do not require pull-up resistors and should be left unconnected by the system to
minimize possible output switching.
The TEST0 pin requires a pull-up resistor of 120
or less connected to GV
DD_OVDD.
Motorola recommends that RTC should have weak pull-up resistors (2–10 k
) connected to GV
DD_OVDD
and that the following signals should be pulled up to GVDD_OVDD with weak pull-up resistors (2–10 k):
SDA, SCL, SMI, SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2,
QACK/DA0, and DRDY.
The following PCI control signals should be pulled up to LVDD (the clamping voltage) with weak pull-up
resistors (2–10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor
values may need to have stronger adjustment to reduce induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
The following pins have internal pull-up resistors that are enabled only while the device is in the reset state:
GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], and PMAA[0:2]. See
Table 17 for more information.
The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the negation of HRST_CPU and HRST_CTRL.
Reset configuration pins should be tied to GND by means of 1-k
pull-down resistors to ensure that a logic
zero level is read into the configuration bits during reset if the default logic-one level is not desired.
Any other unused active low input pins should be tied to a logic-one level by means of weak pull-up resistors
(2–10 k
) to the appropriate power supply listed in Table 17. Unused active high input pins should be tied
to GND by means of weak pull-down resistors (2–10 k
).
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