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參數(shù)資料
| 型號： | MPC8241LZQ266D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357 |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 827K |
| 代理商： | MPC8241LZQ266D |
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MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
15
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
locking range loop delay versus frequency of operation.
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
Register settings that define each DLL mode are shown in Table 9.
21
OSC_IN frequency stability
—
100
ppm
Notes:
1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 through 2.4 V.
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any
intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is,
the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is
locked. While pin-to-pin skew between SDRAM_CLKs can be measured, the relationship between the internal
sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after
a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figure 7 through Figure 10). Tclk is
the period of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagation delay of the DLL synchronization
feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length
(unloaded PC board runner) corresponds to approximately 1 ns of delay. For details about how Figure 7 through
Figure 10 may be used, refer to the Motorola application note AN2164, MPC8245/MPC8241 Memory Clock Design
Guidelines for details about memory clock design on the MPC8245.
7. Rise and fall times for the OSC_IN input are guaranteed by design and characterization. OSC_IN input rise and fall
times are not tested.
Table 9. DLL Mode Definition
DLL Mode
Value of Bit 2 of Config
Register at 0x76
Value of Bit 7 of Config
Register at 0x72
Normal tap delay,
No DLL extend
00
Normal tap delay,
DLL extend
01
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num
Characteristics and Conditions
Min
Max
Unit
Notes
5a
5b
VM
VM = Midpoint Voltage (1.4 V)
2
3
CVIL
CVIH
1
PCI_SYNC_IN
VM
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