參數(shù)資料
型號(hào)： MPC8245ARVV400D
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352
文件頁(yè)數(shù)： 33/68頁(yè)
文件大?。?/td> 1143K
代理商： MPC8245ARVV400D
MPC8245 Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
39
Package Description
DA[14:15]
F1 J2
Output
GVDD
DRV_MEM_CTRL
2, 6
Notes:
1. Place a pull-up resistor of 120
Ω or less on the TEST0 pin.
2. Treat these pins as no connects (NC) unless debug address functionality is used.
3. This pin has an internal pull-up resistor that is enabled only in the reset state. The value of the internal pull-up resistor is not
guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits during reset if the signal is left unterminated.
4. This pin is a reset configuration pin.
5. DL[0] is a reset configuration pin with an internal pull-up resistor that is enabled only in the reset state. The value of the
internal pull-up resistor is not guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits during reset.
6. Multi-pin signals such as AD[31:0] and MDL[0:31] have their physical package pin numbers listed in an order corresponding
to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22, ..., AD31 is on pin V25.
7. GNT4 is a reset configuration pin with an internal pull-up resistor that is enabled only in the reset state.
8. A weak pull-up resistor (2–10 k
Ω) should be placed on this PCI control pin to LV
DD.
9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
10. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to OV
DD.
11. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to GV
DD.
12. This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not guaranteed
but is sufficient to prevent unused inputs from floating.
13. An external PCI clocking source or fan-out buffer may be required for the MPC8245 DUART functionality since PCI_CLK[0:3]
are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.
14. This pin is a multiplexed signal and appears more than once in this table.
15. This pin is affected by the programmable PCI_HOLD_DEL parameter.
16. This pin is an open-drain signal.
17. This pin can be programmed as driven (default) or as open-drain (in MIOCR 1).
18. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.
19. OSC_IN uses the 3.3-V PCI interface driver, which is 5-V tolerant. See Table 2 for details.
20. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation of HRST_CTRL
and HRST_CPU in order to be latched.
21. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals use
DRV_MEM_CLK for chip Rev 1.2 (B).
22. The 266- and 300-MHz part offerings can run at a source voltage of 1.8 ± 100 mV or 2.0 ± 100 mV. Source voltage should
be 2.0 ± 100 mV for 333- and 350-MHz parts.
23. This pin is LAVDD on the MPC8240. It is an NC on the MPC8245, which should not pose a problem when an MPC8240 is
replaced with an MPC8245.
24. The driver capability of this pin is hardwired to 40
Ω and cannot be changed.
25. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to OV
DD so that a 1 can be detected at reset if an external
memory clock is not used and PLL[0:4] does not select a half-clock frequency ratio.
26. Typically, the serial port has sufficient drivers in the RS232 transceiver to drive the CTS pin actively as an input. No pullups
are needed in this case.
27. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the
device to be in the nonreset state
Table 17. MPC8245 Pinout Listing (continued)
Name
Pin Numbers
Type
Power
Supply
Output
Driver Type
Notes
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