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參數(shù)資料
| 型號： | MPC8245ARVV400D |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352 |
| 文件頁數(shù)： | 42/68頁 |
| 文件大?。?/td> | 1143K |
| 代理商： | MPC8245ARVV400D |
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MPC8245 Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
47
System Design
The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the negation of HRST_CPU and HRST_CTRL.
Reset configuration pins should be tied to GND via 1-k
Ω pull-down resistors to ensure a logic 0 level is
read into the configuration bits during reset if the default logic 1 level is not desired.
Any other unused active low input pins should be tied to a logic-one level through weak pull-up resistors
(2–10 k
Ω) to the appropriate power supply listed in Table 17. Unused active high input pins should be tied
to GND through weak pull-down resistors (2–10 k
Ω).
7.5
PCI Reference Voltage—LVDD
The MPC8245 PCI reference voltage (LVDD) pins should be connected to a 3.3 ± 0.3 V power supply if
interfacing the MPC8245 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to a
5.0 V ± 5% power supply if interfacing the MPC8245 into a 5-V PCI bus system. For either reference
voltage, the MPC8245 always performs 3.3-V signaling as described in the PCI Local Bus Specification
(Rev. 2.2). The MPC8245 tolerates 5-V signals when interfaced into a 5-V PCI bus system.
7.6
MPC8245 Compatibility with MPC8240
The MPC8245 AC timing specifications are backward-compatible with those of the MPC8240, except for
the requirements of item 11 in Table 10. Timing adjustments are needed as specified for Tos
(SDRAM_SYNC_IN to sys_logic_clk offset) time requirements.
The MPC8245 does not support the SDRAM flow-through memory interface.
The nominal core VDD power supply changes from 2.5 V on the MPC8240 to 1.8/2.0 V on the MPC8245.
See Table 2.
For example, the MPC8245 PLL_CFG[0:4] setting 0x02 (0b00010) has a different PCI-to-Mem and
Mem-to-CPU multiplier ratio than the same setting on the MPC8240, so it is not backward-compatible.
See Table 18.
Most of the MPC8240 PLL_CFG[0:4] settings are subsets of the PCI_SYNC_IN input frequency range
accepted by the MPC8245. However, the parts are not fully backward-compatible since the ranges of the
two parts do not always match. Modes 0x8 and 0x18 of the MPC8245 are not compatible with settings 0x8
Two reset configuration signals on the MPC8245 are not used as reset configuration signals on the
MPC8240: SDMA0 and SDMA1.
The SDMA0 reset configuration pin selects between the MPC8245 DUART and the MPC8240
backward-compatible mode PCI_CLK[0:4] functionality on these multiplexed signals. The default state
(logic 1) of SDMA0 selects the MPC8240 backward-compatible mode of PCI_CLK[0:4] functionality
while a logic 0 state on the SDMA0 signal selects DUART functionality. In DUART mode, four of the five
PCI clocks, PCI_CLK[0:3], are not available.
The SDMA1 reset configuration pin selects between MPC8245 extended ROM functionality and
MPC8240 backward-compatible functionality on the multiplexed signals: TBEN, CHKSTOP_IN,
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相關代理商/技術參數(shù) |
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| MPC8245ARZU400D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8245ARZU400D | 制造商:Freescale Semiconductor 功能描述:IC 32BIT MPU 400MHZ BGA-352 |
| MPC8245ARZU466D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Part Number Specification for the MPC8245ARZUnnnX Series |
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