參數(shù)資料
型號(hào): MPC8275VR
廠商: Motorola, Inc.
英文描述: PowerQUICC II Family Hardware Specifications
中文描述: 的PowerQUICC II系列硬件規(guī)格
文件頁(yè)數(shù): 13/76頁(yè)
文件大?。?/td> 496K
代理商: MPC8275VR
MOTOROLA
MPC8280 PowerQUICC II Family Hardware Specifications
13
Thermal Characteristics
4.2
Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (
Ψ
JT
) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
T
J
= T
T
+ (
Ψ
JT
×
P
D
)
where:
Ψ
JT
= thermal characterization parameter
T
T
= thermocouple temperature on top of package
P
D
= power dissipation in package
The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge
type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is placed
flat against the case to avoid measurement errors caused by cooling effects of the thermocouple wire.
4.3
Layout Practices
Each V
CC
pin should be provided with a low-impedance path to the board’s power supply. Each ground pin
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on chip. The V
CC
power supply should be bypassed to ground using at least four 0.1 μF
by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip V
CC
and ground should be kept to less than half an inch
per capacitor lead. A four-layer board is recommended, employing two inner layers as V
CC
and GND planes.
All output pins on the MPC8280 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized to minimize overdamped conditions and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data buses. Maximum PC
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as
well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the V
CC
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
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