參數(shù)資料
型號: MPC8275VR
廠商: Motorola, Inc.
英文描述: PowerQUICC II Family Hardware Specifications
中文描述: 的PowerQUICC II系列硬件規(guī)格
文件頁數(shù): 74/76頁
文件大小: 496K
代理商: MPC8275VR
74
MPC8280 PowerQUICC II Family Hardware Specifications
MOTOROLA
Ordering Information
10
Ordering Information
Figure 19 provides an example of the Motorola part numbering nomenclature for the MPC8280. In addition
to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any
enhancement(s) in the part from the original production design. Each part number also contains a revision
code that refers to the die mask revision number and is specified in the part numbering scheme for
identification purposes only. For more information, contact your local Motorola sales office.
Figure 19. Motorola Part Number Key
11
Document Revision History
Table 24. Document Revision History
Revision
Date
Substantive Changes
0.1
Initial public release
0.2
11/2002 Table 22, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63)
0.3
6/2003
Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the
MPC8275VR have local bus support.
References to “G2 core” changed to “G2_LE core.” Refer to the
G2 Core Reference Manual
(G2CORERM/D).
Addition of VCCSYN to “Note” below Table 4, and to note 3 of Table 5
Figure 2: New
Table 5: Addition of note 1
Table 6: Addition of
θ
JB
and
θ
JC
. Modifications to ZU package values.
Table 7: Addition of various configurations, Modification of values. Addition of note 3.
Table 9: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.
Table 10: Addition of 66 MHZ and 100 MHz values
Table 12: sp30 values. sp33b @100 MHz value. Removal of previous note 2. Modification of
current note 2.
Figure 5, Figure 6, Figure 7, and Figure 8: Addition of notes
Section 6.2: Addition of note on PCI timing
Table 15, Table 16, Table 17, Table 18, Table 19: Addition of note 1 concerning minimum
operating frequencies
Addition of statement before clock tables about selection of clock configuration and input
frequency
Table 20 and Table 22: Addition of note 1 to CPM pins
Product Code
Device Number
Package
Processor Frequency
(CPU/CPM/Bus)
Die Revision Level
MPC 82XX C ZU XXX
X
Temperature Range
Blank = 0
TA
to 105
Tj
C = (-40)
TA
– 105
Tj
ZU = 480 TBGA Lead spheres
VR = 516 PBGA Lead-free spheres
ZQ = 516 PBGA Lead spheres
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