參數(shù)資料
型號: MPC8308-KIT
廠商: Freescale Semiconductor
文件頁數(shù): 10/83頁
文件大?。?/td> 0K
描述: KIT EVALUATION FOR MPC830X
標準包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關產(chǎn)品: MPC8308
所含物品: 板,線纜,CD,電源
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
18
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
This figure shows the MII transmit AC timing diagram.
Figure 8. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
This table provides the MII receive AC timing specifications.
Table 24. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD /NVDD of 3.3 V ± 0.3V.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
400
ns
RX_CLK clock period 100 Mbps
tMRX
—40—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0
4.0
ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference
(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
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