參數(shù)資料
型號(hào)： MPC8308-KIT
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 5/83頁(yè)
文件大?。?/td> 0K
描述： KIT EVALUATION FOR MPC830X
標(biāo)準(zhǔn)包裝： 1
系列： PowerQUICC II™ PRO
類型： MPU
適用于相關(guān)產(chǎn)品： MPC8308
所含物品： 板，線纜，CD，電源
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
13
DDR2 SDRAM
MDQ//MDM/MECC output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
—ps
5
266 MHz
900
MDQ//MDM/MECC output hold with respect to
MDQS
tDDKHDX,
tDDKLDX
—ps
5
266 MHz
1100
MDQS preamble start
tDDKHMP
0.75 x tMCK
—ns
6
MDQS epilogue end
tDDKHME
0.4 x tMCK
0.6 x tMCK
ns
6
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. For a description and understanding of the timing modifications enabled by use of these bits, see the
MPC8308 PowerQUICC II Pro Processor Reference Manual.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Table 18. DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8308-NSG 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 MPC8308-NSG RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8308-NSG 制造商:Freescale Semiconductor 功能描述:MPC8308-NSG*NIC*
MPC8308-RDB 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 Refer. Board MPC8308 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8308-RDB-PROMO 制造商:Freescale 功能描述:Motherboards MPC8308 PowerQuicc II DDR2 10Mbps/100Mbps/1000Mbps Linux Kernel
MPC8308-SOM 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 For MPC8308 Ethernet USB 32bit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
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