參數(shù)資料
型號: MPC8308-KIT
廠商: Freescale Semiconductor
文件頁數(shù): 2/83頁
文件大?。?/td> 0K
描述: KIT EVALUATION FOR MPC830X
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8308
所含物品: 板,線纜,CD,電源
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
10
Freescale Semiconductor
DDR2 SDRAM
6DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface. Note that
DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) when
GVDD(typ) = 1.8 V.
This table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
1.7
1.9
V
1
I/O reference voltage
MVREF
0.49
GV
DD
0.51
GV
DD
V2
I/O termination voltage
VTT
MVREF –0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.125
GVDD +0.3
V
Input low voltage
VIL
–0.3
MVREF –0.125
V
Output leakage current
IOZ
–9.9
9.9
A4
Output high current (VOUT = 1.420 V)
IOH
–13.4
mA
Output low current (VOUT = 0.280 V)
IOL
13.4
mA
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT GVDD.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
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