參數(shù)資料
型號(hào)： MPC8313EVRAGDB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516
文件頁(yè)數(shù)： 39/100頁(yè)
文件大?。?/td> 1247K
代理商： MPC8313EVRAGDB
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
43
High-Speed Serial Interfaces (HSSI)
Figure 30 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the MPC8313E SerDes reference clock
input’s DC requirement.
Figure 30. Single-Ended Connection (Reference Only)
9.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low-phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50
Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 40 describes some AC parameters for SGMII protocol.
Table 40. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.0 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising edge rate
Rise edge rate
1.0
4.0
V/ns
2, 3
Falling edge rate
Fall edge rate
1.0
4.0
V/ns
2, 3
Differential input high voltage
VIH
+200
—
mV
2
Differential input low voltage
VIL
—
–200
mV
2
SD
n_REF_CLK
SD
n_REF_CLK
100
Ω Differential PWB Trace
Clock Driver
CLK_Out
Single-Ended CLK
Driver Chip
MPC8313E
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
50
Ω
SerDes Refer.
CLK Receiver
50
Ω
50
Ω
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