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  • 參數(shù)資料
    型號(hào): MPC8313EVRAGDB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA516
    封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-516
    文件頁(yè)數(shù): 78/100頁(yè)
    文件大?。?/td> 1247K
    代理商: MPC8313EVRAGDB
    MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
    Freescale Semiconductor
    79
    Clocking
    Table 65 provides the operating frequencies for the MPC8313E TEPBGAII under recommended operating
    conditions (see Table 2).
    20.1
    System PLL Configuration
    The system PLL is controlled by the RCWL[SPMF] parameter. Table 66 shows the multiplication factor
    encodings for the system PLL.
    Table 64. Configurable Clock Units
    Unit
    Default
    Frequency
    Options
    TSEC1
    csb_clk
    Off,
    csb_clk, csb_clk/2, csb_clk/3
    TSEC2
    csb_clk
    Off,
    csb_clk, csb_clk/2, csb_clk/3
    Security Core, I2C, SAP, TPR
    csb_clk
    Off,
    csb_clk, csb_clk/2, csb_clk/3
    USB DR
    csb_clk
    Off,
    csb_clk, csb_clk/2,
    csb_clk/3
    PCI and DMA complex
    csb_clk
    Off,
    csb_clk
    Table 65. Operating Frequencies for TEPBGAII
    Characteristic1
    Maximum
    Operating Frequency
    Unit
    e300 core frequency (
    core_clk)333
    MHz
    Coherent system bus frequency (
    csb_clk)167
    MHz
    DDR1/2 memory bus frequency (MCK)2
    167
    MHz
    Local bus frequency (LCLK
    n)3
    66
    MHz
    PCI input frequency (SYS_CLK_IN or PCI_CLK)
    66
    MHz
    Notes:
    1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be
    chosen such that the resulting
    csb_clk, MCK, LCLK[0:1], and core_clk frequencies do not
    exceed their respective maximum or minimum operating frequencies. The value of
    SCCR[ENCCM] and SCCR[USBDRCM] must be programmed such that the maximum
    internal operating frequency of the security core and USB modules do not exceed their
    respective value listed in this table.
    2. The DDR data rate is 2x the DDR memory bus frequency.
    3. The local bus frequency is 1/2, 1/4, or 1/8 of the
    lbc_clk frequency (depending on
    LCCR[CLKDIV]), which is in turn, 1x or 2x the
    csb_clk frequency (depending on
    RCWL[LBCM]).
    Table 66. System PLL Multiplication Factors
    RCWL[SPMF]
    System PLL
    Multiplication Factor
    0000
    Reserved
    0001
    Reserved
    0010
    × 2
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