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| 型號： | MPC8540VT833LC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 55/104頁 |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC III 783FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 833MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8540 Integrated Processor Hardware Specifications, Rev. 4.1
54
Freescale Semiconductor
RapidIO
13 RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8540.
13.1 RapidIO DC Electrical Characteristics
respectively.
HRESET to PCI-X initialization pattern hold time
tPCRHIX
050
ns
6, 12
Notes:
1.See the timing measurement conditions in the PCI-X 1.0a Specification.
2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test
point and load circuit.
3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.
4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same
time.
6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access,
tPCRHFV). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no
later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is
asserted.
7.A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In
conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock
frequency.
8.Device must meet this specification independent of how many outputs switch simultaneously.
9.The timing parameter tPCIVKH is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the PCI-X 1.0a
Specification.
10.The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a
Specification.
11.Guaranteed by characterization.
12.Guaranteed by design.
Table 45. RapidIO 8/16 LP-LVDS Driver DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Characteristic
Symbol
Min
Max
Unit
Notes
Differential output high voltage
VOHD
247
454
mV
1, 2
Differential output low voltage
VOLD
–454
–247
mV
1, 2
Differential offset voltage
ΔV
OSD
—50
mV
1,3
Output high common mode voltage
VOHCM
1.125
1.375
V
1, 4
Output low common mode voltage
VOLCM
1.125
1.375
V
1, 5
Table 44. PCI-X AC Timing Specifications at 133 MHz (continued)
Parameter
Symbol
Min
Max
Unit
Notes
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