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| 型號： | MPC8572LPXATLD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 137/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 1023-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.2GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤 |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
98
Freescale Semiconductor
Serial RapidIO
specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE
802.3ae-2002 is recommended as a reference for additional information on jitter test methods.
17.8.1
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point
at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the
Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial
link shall be active in both the transmit and receive directions, and opposite ends of the links shall use
asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane
implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The
amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10-12.
The eye pattern shall be measured with AC coupling and the compliance template centered at 0 Volts
differential. The left and right edges of the template shall be aligned with the mean zero crossing points of
the measured data eye. The load for this test shall be 100
Ω resistive +/– 5% differential to 2.5 GHz.
17.8.2
Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud
Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter
Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial link shall
be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous
clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations
shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured
with AC coupling and at 0 Volts differential. Jitter measurement for the transmitter (or for calibration of a
jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that
described in Annex 48B of IEEE 802.3ae.
17.8.3
Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100
Ω resistive +/– 5%
differential to 2.5 GHz.
17.8.4
Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first
producing the sum of deterministic and random jitter defined in Section 17.6, “Receiver Specifications,”
and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening
of the receive template shown in Figure 60 and Table 75. Note that for this to occur, the test signal must
have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random
jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade
roll-off below this. The required sinusoidal jitter specified in Section 17.6, “Receiver Specifications,” is
then added to the signal and the test load is replaced by the receiver being tested.
相關(guān)PDF資料 |
PDF描述 |
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| 396-020-541-804 | CARD EDGE 20POS DL .125X.250 BLK |
| 396-020-541-802 | CARD EDGE 20POS DL .125X.250 BLK |
| MPC8572LPXARLD | MPU POWERQUICC III 1023-PBGA |
| 396-020-541-204 | CARD EDGE 20POS DL .125X.250 BLK |
| MPC8572EVTAVNB | MPU POWERQUICC III 1023-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8572LPXATLE | 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1200LP - Bulk |
| MPC8572LPXAULD | 功能描述:微處理器 - MPU CSM SNPB 1333 LOW PWR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572LPXAULE | 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1333LP - Bulk |
| MPC8572LPXAVND | 功能描述:微處理器 - MPU CSM SNPB 1500 LOW PWR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572LPXAVNE | 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1500LP - Bulk |
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