參數(shù)資料
型號: MPC8572LPXATLD
廠商: Freescale Semiconductor
文件頁數(shù): 83/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
49
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.4
eTSEC IEEE Std 1588 AC Specifications
Figure 26 shows the data and command output timing diagram.
Figure 26. eTSEC IEEE 1588 Output AC Timing
1 The output delay is count starting rising edge if t
T1588CLKOUT is non-inverting. Otherwise, it is count starting falling edge.
Figure 27 shows the data and command input timing diagram.
Figure 27. eTSEC IEEE 1588 Input AC timing
Table 42 provides the IEEE 1588 AC timing specifications.
Table 42. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK clock period
tT1588CLK
3.3
TTX_CLK*9
ns
1
TSEC_1588_CLK duty cycle
tT1588CLKH
/tT1588CLK
40
50
60
%
TSEC_1588_CLK peak-to-peak jitter
tT1588CLKINJ
——
250
ps
Rise time eTSEC_1588_CLK (20%–80%)
tT1588CLKINR
1.0
2.0
ns
Fall time eTSEC_1588_CLK (80%–20%)
tT1588CLKINF
1.0
2.0
ns
TSEC_1588_CLK_OUT clock period
tT1588CLKOUT
2*tT1588CLK
——ns
TSEC_1588_CLK_OUT
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
tT1588OV
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
tT1588CLK
tT1588CLKH
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