參數(shù)資料
型號(hào): MPC8572LPXATLD
廠商: Freescale Semiconductor
文件頁數(shù): 7/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
104
Freescale Semiconductor
Package Description
LGPL2/LOE/LFRE
UPM General Purpose Line 2 /
Output Enable / Flash Read
Enable
A27
O
BVDD
5, 8, 9
LGPL3/LFWP
UPM General Purpose Line 3 /
Flash Write Protect
K16
O
BVDD
5, 9
LGPL4/LGTA/LUPWAIT/LPBSE
/LFRB
UPM General Purpose Line 4 /
Target Ack / Wait / Parity Byte
Select / Flash Ready-Busy
L17
I/O
BVDD
LGPL5
UPM General Purpose Line 5 /
Amux
B26
O
BVDD
5, 9
LCLK[0:2]
Local Bus Clock
F17, F16, A23
O
BVDD
LSYNC_IN
Local Bus DLL Synchronization B22
I
BVDD
LSYNC_OUT
Local Bus DLL Synchronization A21
O
BVDD
DMA
DMA1_DACK[0:1]
DMA Acknowledge
W25, U30
O
OVDD
21
DMA2_DACK[0]
DMA Acknowledge
AA26
O
OVDD
5, 9
DMA1_DREQ[0:1]
DMA Request
Y29, V27
I
OVDD
DMA2_DREQ[0]
DMA Request
V29
I
OVDD
DMA1_DDONE[0:1]
DMA Done
Y28, V30
O
OVDD
5, 9
DMA2_DDONE[0]
DMA Done
AA28
O
OVDD
5, 9
DMA2_DREQ[2]
DMA Request
M23
I
BVDD
Programmable Interrupt Controller
UDE0
Unconditional Debug Event
Processor 0
AC25
I
OVDD
UDE1
Unconditional Debug Event
Processor 1
AA25
I
OVDD
MCP0
Machine Check Processor 0
M28
I
OVDD
MCP1
Machine Check Processor 1
L28
I
OVDD
IRQ[0:11]
External Interrupts
T24, R24, R25, R27,
R28, AB27, AB28, P27,
R30, AC28, R29, T31
IOVDD
IRQ_OUT
Interrupt Output
U24
O
OVDD
2, 4
1588
TSEC_1588_CLK
Clock In
AM22
I
LVDD
TSEC_1588_TRIG_IN
Trigger In
AM23
I
LVDD
Table 76. MPC8572E Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
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