" />
參數資料
型號： MPC8572LPXATLD
廠商： Freescale Semiconductor
文件頁數： 91/138頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023-PBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.2GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應商設備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
56
Freescale Semiconductor
Local Bus Controller (eLBC)
Table 51 describes the general timing parameters of the local bus interface at BVDD = 1.8 V DC
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—2.5
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—2.4
ns
3
Local bus clock to LALE assertion
tLBKHOV4
—2.4
ns
3
Output hold from local bus clock (except LAD/LDP and
LALE)
tLBKHOX1
0.8
—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
0.8
—
ns
3
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
tLBKHOZ1
—2.6
ns
5
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ2
—2.6
ns
5
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock
reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the
tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock
for PLL bypass mode to 0.4
× BVDD of the signal in question for 2.5-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT
is programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
8. Guaranteed by design.
Table 51. Local Bus General Timing Parameters (BVDD = 1.8 V DC)—PLL Enabled
At recommended operating conditions with BVDD of 1.8 V ± 5%
Parameter
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
6.67
12
ns
2
Local bus duty cycle
tLBKH/tLBK
43
57
%
—
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
—
150
ps
7, 8
Input setup to local bus clock (except LGTA/LUPWAIT)
tLBIVKH1
2.4
—
ns
3, 4
LGTA/LUPWAIT input setup to local bus clock
tLBIVKH2
1.9
—
ns
3, 4
Input hold from local bus clock (except LGTA/LUPWAIT)
tLBIXKH1
1.1
—
ns
3, 4
LGTA/LUPWAIT input hold from local bus clock
tLBIXKH2
1.1
—
ns
3, 4
LALE output negation to high impedance for LAD/LDP
(LATCH hold time)
tLBOTOT
1.2
—
ns
6
Table 50. Local Bus General Timing Parameters (BVDD = 2.5 V DC)—PLL Enabled (continued)
At recommended operating conditions with BVDD of 2.5 V ± 5% (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
相關PDF資料
PDF描述
396-020-541-804 CARD EDGE 20POS DL .125X.250 BLK
396-020-541-802 CARD EDGE 20POS DL .125X.250 BLK
MPC8572LPXARLD MPU POWERQUICC III 1023-PBGA
396-020-541-204 CARD EDGE 20POS DL .125X.250 BLK
MPC8572EVTAVNB MPU POWERQUICC III 1023-PBGA
相關代理商/技術參數
參數描述
MPC8572LPXATLE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1200LP - Bulk
MPC8572LPXAULD 功能描述:微處理器 - MPU CSM SNPB 1333 LOW PWR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572LPXAULE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1333LP - Bulk
MPC8572LPXAVND 功能描述:微處理器 - MPU CSM SNPB 1500 LOW PWR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572LPXAVNE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1500LP - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*