參數(shù)資料
型號: MPC8572LPXATLD
廠商: Freescale Semiconductor
文件頁數(shù): 80/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
46
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 23. SGMII Transmitter DC Measurement Circuit
Table 39 lists the SGMII DC receiver electrical characteristics.
Table 39. SGMII DC Receiver Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply Voltage
XVDD_SRDS2
1.045
1.1
1.155
V
DC Input voltage range
N/A
1
Input differential voltage
LSTS = 0
VRX_DIFFp-p
100
1200
mV
2, 4
LSTS = 1
175
Loss of signal threshold
LSTS = 0
VLOS
30
100
mV
3, 4
LSTS = 1
65
175
Input AC common mode voltage
VCM_ACp-p
—100
mV
5
Receiver differential input impedance
ZRX_DIFF
80
100
120
Ω
Receiver common mode input
impedance
ZRX_CM
20
35
Ω
Common mode input voltage
VCM
—Vxcorevss
—V
6
Note:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak to peak input differential voltage
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to
PCI Express Differential Receiver (RX) Input Specifications section for further explanation.
4. The LSTS shown in the table refers to the LSTSAB or LSTSEF bit field of MPC8572E’s SerDes 2 Control Register.
5. VCM_ACp-p is also referred to as peak to peak AC common mode voltage.
6. On-chip termination to SGND_SRDS2 (xcorevss).
50
Ω
Transmitter
SD2_TXn
50
Ω
Vos
VOD
MPC8572E SGMII
SerDes Interface
50
Ω
50
Ω
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