
27-8
MPC866 PowerQUICC Family User’s Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SCC Ethernet Channel Frame Reception
27.6
SCC Ethernet Channel Frame Reception
The ethernet receiver handles address recognition and performs CRC, short frame,
maximum DMA transfer, and maximum frame length checking with almost no core
intervention. When the core enables the ethernet receiver, it enters hunt mode as soon as
RENA is asserted while CLSN is negated. In hunt mode, as data is shifted into the receive
shift register one bit at a time, the register contents are compared to the contents of the
SYN1 eld in the data synchronization register (DSR). This compare function becomes
valid a certain number of clocks after the start of the frame (depending on PSMR[NIB]). If
the two are not equal, the next bit is shifted in and the comparison is repeated. If a
double-zero or double-one fault is detected between bits 14 to 21 from the rst received
preamble bit, the frame is rejected. If a double-zero fault is detected after 21 bits from the
rst received preamble bit and before detection of the start frame delimiter (SFD), the frame
is also rejected. When the incoming pattern is not rejected and matches the DSR, the SFD
has been detected; hunt mode is terminated and character assembly begins.
When the receiver detects the rst bytes of the frame, the ethernet controller performs
address recognition on the frame. The receiver can receive physical (individual), group
(multicast), and broadcast addresses. Ethernet receive frame data is not written to memory
until the internal address recognition process completes, which improves bus usage with
frames not addressed to this station. The receiver also operates with an external CAM. With
an external CAM, frame reception continues normally, unless the CAM specically signals
If a match is found, the ethernet controller fetches the next RxBD and, if it is empty, starts
transferring the incoming frame to the RxBD associated data buffer. If a collision is
detected during the frame, the RxBDs associated with this frame are reused. Thus, there
will be no collision frames presented to you except late collisions, which indicate serious
LAN problems. When the data buffer has been lled, the ethernet controller clears the E bit
in the RxBD and generates an interrupt if the I bit is set. If the incoming frame exceeds the
length of the data buffer, the ethernet controller fetches the next RxBD in the table and, if
it is empty, continues transferring the rest of the frame to this buffer. The RxBD length is
determined by MRBLR in the SCC general-purpose parameter RAM, which should be at
least 64 bytes.
During reception, the ethernet controller checks for a frame that is either too short or too
long. When the frame ends, the receive CRC eld is checked and written to the buffer. The
data length written to the last BD in the ethernet frame is the length of the entire frame and
it enables the software to correctly recognize the frame-too-long condition.
When the receive frame is complete, the ethernet controller can sample one byte from the
port B parallel I/O and append this byte to the end of the last RxBD in the frame. For any
PB[16–23] pins dened as outputs, the contents of the PBDAT latch is read instead of the