
MOTOROLA
Chapter 7. Instruction and Data Caches
7-33
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Debug Support
After the caches are initialized, all the cache blocks are invalidated, and the LRU bits point
to way 0 of each set.
7.8
Debug Support
The MPC866 can be debugged either in debug mode or by a software monitor debugger. In
both cases the core of the MPC866 asserts the internal freeze signal. See
Chapter 45,support.
7.8.1
Instruction and Data Cache Operation in Debug Mode
The development system interface of the MPC866 uses the development port, which is a
dedicated serial port. The development port is a relatively inexpensive interface that allows
a development system to operate in a lower frequency than the core’s frequency and
When the MPC866 is in debug mode, all instructions are fetched from the development
port, regardless of the address generated by the MPC866 core. Therefore, the instruction
cache is bypassed when the MPC866 is in debug mode. In addition, the data cache is frozen
in debug mode. Loads and stores in debug mode always target system memory, regardless
of whether the accessed data is resident in the data cache. The only way to access the
contents of the instruction or data cache in debug mode is by using the IC_DAT or DC_DAT
registers.
7.8.2
Instruction and Data Cache Operation with a Software
Monitor Debugger
With debug mode disabled, a software monitor debugger can use the development support
When the internal freeze signal is asserted during run-time, the instruction cache treats all
misses as if they were from cache-inhibited regions. Misses are loaded only into the burst
buffer; hits are loaded from the cache array and the LRU bits are updated. If the debug
routine is not in the instruction cache, it is loaded from memory like any other miss and the
cache state remains the same as before the freeze signal was asserted.
For performance reasons, it may be preferable to run the debug routine from the cache. To
load the debug routine into the instruction cache before entering debug mode, perform the
following procedure:
1. Save all four ways of the sets that are needed for the debug routine by reading the
tag, the LRU, valid, and lock bit states