
MOTOROLA
Chapter 29. Serial Management Controllers (SMCs)
29-11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SMC in UART Mode
4. Execute the rfi instruction.
29.3 SMC in UART Mode
SMCs generally offer less functionality and performance in UART mode than do SCCs,
which makes them more suitable for simpler debug/monitor ports instead of full-featured
UARTs. SMCs do not support the following features in UART mode:
RTS, CTS, and CD signals
Receive and transmit sections clocked at different rates
Fractional stop bits
Built-in multidrop modes
Freeze mode for implementing flow control
Isochronous operation (1
× clock) (That is, a 16× clock is required.)
Interrupts on special control character reception
Ability to transmit data on demand using the TODR
SCCS register to determine idle status of the receive pin
Other features for the SCCs as described in the GSMR
However, the SMC UART frame format, shown in
Figure 29-5, allows a data length of up
to 14 bits. The SCC format supports only up to 8 bits.
Figure 29-5. SMC UART Frame Format
29.3.1 SMC UART Features
The following list summarizes the main features of the SMC in UART mode:
Flexible message-oriented data structure
Programmable data length (5–14 bits)
Programmable 1 or 2 stop bits
Even/odd/no parity generation and checking
Frame error, break, and IDLE detection
Transmit preamble and break sequences
SMCLK
SMTXD
16x
Start
Bit
Parity
Bit
(Optional)
5 to 14 Data Bits with the
Least Significant Bit First
1 or 2
Stop Bits
NOTE:
1. Clock is not to scale.