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參數(shù)資料
| 型號(hào)： | MPC92439EIR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER LVPECL 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.5x11.5） |
| 包裝： | 帶卷 (TR) |
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MPC92439 Data Sheet
900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER
MPC92439 REVISION 5 FEBRUARY 6, 2013
4
2013 Integrated Device Technology, Inc.
Table 1. Pin Configurations
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
6
Analog
Crystal oscillator interface
FREF_EXT
Input
0
LVCMOS Alternative PLL reference input
FOUT, FOUT
Output
LVPECL Differential clock output
TEST
Output
LVCMOS Test and device diagnosis output
XTAL_SEL
Input
1
LVCMOS PLL reference select input
PWR_DOWN
Input
0
LVCMOS Configuration input for power down mode. Assertion (deassertion) of power down will
decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps.
PWR_DOWN assertion (deassertion) is synchronous to the input reference clock.
S_LOAD
Input
0
LVCMOS Serial configuration control input. This inputs controls the loading of the configuration
latches with the contents of the shift register. The latches will be transparent when this
signal is high, thus the data must be stable on the high-to-low transition.
P_LOAD
Input
1
LVCMOS Parallel configuration control input. this input controls the loading of the configuration
latches with the content of the parallel inputs (M and N). The latches will be
transparent when this signal is low, thus the parallel data must be stable on the low-
to-high transition of P_LOAD. P_LOAD is state sensitive.
S_DATA
Input
0
LVCMOS Serial configuration data input.
S_CLOCK
Input
0
LVCMOS Serial configuration clock input.
M[0:6]
Input
1
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD.
OE
Input
1
LVCMOS Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of runt
pulses on the FOUT output. OE = L low stops FOUT in the logic low state (FOUT = L,
FOUT = H).
GND
Supply
Ground
Negative power supply (GND).
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive
power supply for correct operation.
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply).
NC
Do not connect
Table 2. Output Frequency Range and PLL Post-Divider N
PWR_DOWN
N
VCO Output Frequency Division
FOUT Frequency Range
1
0
0
2
200 - 450 MHz
0
1
4
100 -225 MHz
0
1
0
8
50-112.5 MHz
0
1
400-900 MHz
1
0
32
12.5-28.125 MHz
1
0
1
64
6.25-14.0625 MHz
1
0
128
3.125-7.03125 MHz
1
16
25-56.25 MHz
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