參數(shù)資料
型號(hào)： MPC92439EIR2
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 16/16頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER LVPECL 28-PLCC
標(biāo)準(zhǔn)包裝： 500
類型： 時(shí)鐘/頻率合成器
PLL： 是
輸入： 晶體
輸出： LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 900MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.5x11.5）
包裝： 帶卷 (TR)
MPC92439 Data Sheet
900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER
MPC92439 REVISION 5 FEBRUARY 6, 2013
9
2013 Integrated Device Technology, Inc.
transition on the S_LOAD input will latch the new divide values into
the counters. Figure 7 illustrates the timing diagram for both a
parallel and a serial load of the MPC92439 synthesizer.
M[6:0] and N[1:0] are normally specified once at power-up
through the parallel interface, and then possibly again through the
serial interface. This approach allows the application to come up at
one frequency and then change or fine-tune the clock as the ability
to control the serial interface becomes available.
Using the Test and Diagnosis Output TEST
The TEST output provides visibility for one of the several internal
nodes as determined by the T[2:0] bits in the serial configuration
stream. It is not configurable through the parallel interface. Although
it is possible to select the node that represents FOUT, the LVCMOS
output is not able to toggle fast enough for higher output frequencies
and should only be used for test and diagnosis.
The T2, T1 and T0 control bits are preset to ‘000' when P_LOAD
is LOW so that the PECL FOUT outputs are as jitter-free as possible.
Any active signal on the TEST output pin will have detrimental
affects on the jitter of the PECL output pair. In normal operations,
jitter specifications are only guaranteed if the TEST output is static.
The serial configuration port can be used to select one of the
alternate functions for this pin.
Most of the signals available on the TEST output pin are useful
only for performance verification of the MPC92439 itself. However,
the PLL bypass mode may be of interest at the board level for
functional debug. When T[2:0] is set to 110 the MPC92439 is placed
in PLL bypass mode. In this mode the S_CLOCK input is fed directly
into the M and N dividers. The N divider drives the FOUT differential
pair and the M counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level functional
test or debug. Bypassing the PLL and driving FOUT directly gives
the user more control on the test clocks sent through the clocktree
shows the functional setup of the PLL bypass mode. Because the
S_CLOCK is a CMOS level the input frequency is limited to 200
MHz. This means the fastest the FOUT pin can be toggled via the
S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is
2 (if N = 1). Note that the M counter output on the TEST output will
not be a 50% duty cycle.
Figure 7. Serial Interface Timing Diagram
Power Supply Filtering
The MPC92439 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if this
noise is seen on the power supply pins. Random noise on the
VCC_PLL pin impacts the device characteristics. The MPC92439
provides separate power supplies for the digital circuitry (VCC) and
the internal PLL (VCC_PLL) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked loop. In a
controlled environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system environment
where it is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simplest form of
isolation is a power supply filter on the VCC_PLL pin for the
MPC92439. Figure 8 illustrates a typical power supply filter scheme.
The MPC92439 is most susceptible to noise with spectral content in
the 1 kHz to 1 MHz range. Therefore, the filter should be designed
to target this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop that will be seen between
Table 10. Test and Debug Configuration for TEST
T[2:0]
TEST Output
T2
T1
T0
000
12-bit shift register out(1)
1. Clocked out at the rate of S_CLOCK\
0
1
Logic 1
010
fXTAL 2
0
1
M-Counter out
1
0
FOUT
1
0
1
Logic 0
1
0
M-Counter out in PLL-bypass mode
1
FOUT
4
Table 11. Debug Configuration for PLL Bypass(1)
1. T[2:0] = 110. AC specifications do not apply in PLL bypass
mode
Output
Configuration
FOUT
S_CLOCK
N
TEST
M-Counter out(2)
2. Clocked out at the rate of S_CLOCK
(2N)
S_CLOCK
S_DATA
S_LOAD
M[6:0]
N[1:0]
P_LOAD
T2 T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
M, N
First
Bit
Last
Bit
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