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參數(shù)資料
| 型號： | MPC92439EIR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 28-PLCC |
| 標準包裝： | 500 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.5x11.5） |
| 包裝： | 帶卷 (TR) |
MPC92439 Data Sheet
900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER
MPC92439 REVISION 5 FEBRUARY 6, 2013
8
2013 Integrated Device Technology, Inc.
PROGRAMMING INTERFACE
Programming the MPC92439
Programming the MPC92439 amounts to properly configuring the
internal PLL dividers to produce the desired synthesized frequency
at the output. The output frequency can be represented by this
formula:
fOUT = fXTAL M N
(1)
where fXTAL is the crystal frequency, M is the PLL feedback-divider
and N is the PLL post-divider. The input frequency and the selection
of the feedback divider M is limited by the VCO-frequency range.
fXTAL and M must be configured to match the VCO frequency range
of 400 to 900 MHz in order to achieve stable PLL operation:
MMIN = fVCO,MIN (fXTAL) and
(2)
MMAX = fVCO,MAX (fXTAL)
(3)
For instance, the use of a 16 MHz input frequency requires the
configuration of the PLL feedback divider between M = 25 and M =
56. Table 8 shows the usable VCO frequency and M divider range for
other example input frequencies. Assuming that a 16 MHz input
frequency is used, equation (1) reduces to:
fOUT = 16 M N
(4)
Substituting N for the four available values for N (1, 2, 4, 8) yields:
Example Calculation for an 16 MHz Input Frequency
For example, if an output frequency of 384 MHz was desired, the
following steps would be taken to identify the appropriate M and N
values. 384 MHz falls within the frequency range set by an N value
of 2, so N[1:0]=00. For N = 2, FOUT = 8M and M = FOUT
8.
Therefore, M = 384
8 = 48, so M[6:0] = 0110000. Following this
procedure a user can generate any whole frequency between 50
MHz and 900 MHz. The size of the programmable frequency steps
will be equal to:
fSTEP = fXTAL N
(5)
APPLICATIONS INFORMATION
Jitter Performance of the MPC92439
Figure 5 and Figure 6 illustrate the RMS jitter performance of the
MPC92439 across its specified VCO frequency range. The cycle-to-
cycle and period jitter is a function of the VCO frequency and the
output divider N. The general trend is that as the output frequency
increases (higher VCO frequency and lower N-divider) the
MPC92439 output jitter decreases. Optimum jitter performance can
be achieved at higher VCO and output frequencies. The maximum
cycle-to-cycle and period jitter published in Table 7 correspond to the
jitter performance at the lowest VCO frequency limit).
Figure 5. MPC92439 Cycle-to-cycle Jitter
Figure 6. MPC92439 Period Jitter
Using the Parallel and Serial Interface
The M and N counters can be loaded either through a parallel or
serial interface. The parallel interface is controlled via the P_LOAD
signal such that a LOW to HIGH transition will latch the information
present on the M[6:0] and N[1:0] inputs into the M and N counters.
When the P_LOAD signal is LOW the input latches will be
transparent and any changes on the M[6:0] and N[1:0] inputs will
affect the FOUT output pair. To use the serial port the S_CLOCK
signal samples the information on the S_DATA line and loads it into
a 12 bit shift register. Note that the P_LOAD signal must be HIGH for
the serial load operation to function. The Test register is loaded with
the first three bits, the N register with the next two, and the M register
with the final eight bits of the data stream on the S_DATA input. For
each register the most significant bit is loaded first (T2, N1 and M6).
A pulse on the S_LOAD pin after the shift register is fully loaded will
transfer the divide values into the counters. The HIGH to LOW
Table 9. Output Frequency Range for fXTAL = 16 MHz
N
FOUT
FOUT Range
FOUT Step
1
0
Value
00
2
8
M
200-450 MHz
8 MHz
01
4
M
100-225 MHz
4 MHz
10
8
2
M
50-112.5 MHz
2 MHz
11
1
16
M
400-900 MHz
16 MHz
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相關代理商/技術參數(shù) |
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| MPC92439FA | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
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| MPC92469AC | 功能描述:時鐘合成器/抖動清除器 LVPECL Clock Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92469ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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