MPC951
TIMING SOLUTIONS
BR1333 — Rev 6
3
MOTOROLA
FUNCTION TABLE – MPC951
INPUTS
OUTPUTS
TOTALS
fsela
fselb
fselc
fseld
Qa(1)
Qb(1)
Qc(2)
Qd(5)
Total 2x
Total x
Total x/2
0
2x
x
1
8
0
1
2x
x
x/2
1
3
5
0
1
0
2x
x
x/2
x
1
6
2
0
1
2x
x
x/2
1
7
0
1
0
2x
x/2
x
1
7
1
0
1
0
1
2x
x/2
x
x/2
1
2
6
0
1
0
2x
x/2
x
1
3
5
0
1
2x
x/2
1
0
8
1
0
x
0
9
0
1
0
1
x
x/2
0
4
5
1
0
1
0
x
x/2
x
0
7
2
1
0
1
x
x/2
0
2
7
1
0
x
x/2
x
0
8
1
0
1
x
x/2
x
x/2
0
3
6
1
0
x
x/2
x
0
6
3
1
x
x/2
0
1
8
NOTE: x = fVCO/4; 200MHz < fVCO < 480MHz.
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VCC + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
–40
125
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive
capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die
power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application
note AN1545.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
LVCMOS Inputs
2.0
3.6
V
VIL
Input LOW Voltage
LVCMOS Inputs
0.8
V
VPP
Peak–to–Peak Input Voltage
PECL_CLK
300
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC–2.0
VCC–0.6
V
Note 1.
VOH
Output HIGH Voltage
2.4
V
IOH = –40mA, Note 2.
VOL
Output LOW Voltage
0.5
V
IOL = 40mA, Note 2.
IIN
Input Current
±120
A
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
25
pF
Per Output
ICC
Maximum Quiescent Supply Current
90
115
mA
All VCC Pins
ICCPLL
Maximum PLL Supply Current
15
20
mA
VCCA Pin Only
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
the VCMR range and the input swing lies within the VPP specification.
2. The MPC951 outputs can drive series or parallel terminated 50
(or 50 to VCC/2) transmission lines on the incident edge (see Applications
Info section).
MPC951
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC951
3