240
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
The conversion takes advantage of the amplifier characteristics to ensure minimum conversion time.
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion is started. In order
to have a better understanding of the functioning of the amplifier synchronization, a timing diagram example is
In case the amplifier output is modified during the sample phase of the ADC, the on-going conversion is aborted
and restarted as soon as the output of the amplifier is stable as shown
Figure 20-16.
The only precaution to take is to be sure that the trig signal (PSC) frequency is lower than ADCclk/4.
t is also possible to auto trigger conversion on the amplified channel. In this case, the conversion is started at the
next amplifier clock event following the last auto trigger event selected thanks to the ADTS bits in the ADCSRB
register. In auto trigger conversion, the free running mode is not possible unless the ADSC bit in ADCSRA is set by
soft after each conversion.
Only PSC sources can auto trigger amplified conversion. In this case, the core must have a clock synchronous with
the PSC; if the PSC uses the PLL clock, the core must use PLL/4 clock source.
Figure 20-15. Amplifier synchronization timing diagram with change on analog input signal.
Valid sample
Delta V
4th stable sample
Signal to be
measured
AMPLI_clk
(Sync Clock)
CK ADC2
Amplifier Sample
Enable
Amplifier Hold
Value
PSCn_ASY
PSC
Block
Amplifier
Block
ADSC
ADC
Activity
ADC
Sampling
ADC
Conv
ADC
Sampling
ADC
Conv
ADC Result
Ready
ADC Result
Ready