89
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f
clk_I/O/8)
13.8
8-bit Timer/Counter Register Description
13.8.1
Timer/Counter Control Register A – TCCR0A
Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the
OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting.
Table 13-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-
PWM).
Table 13-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
7
6
5
4
3
210
COM0A1
COM0A0
COM0B1
COM0B0
–
WGM01
WGM00
TCCR0A
Read/Write
R/W
R
R/W
Initial Value
0
Table 13-2.
Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match
1
Set OC0A on Compare Match
Table 13-3.
Compare Output Mode, Fast PWM Mode
(1)COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
01
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match, set OC0A at TOP
1
Set OC0A on Compare Match, clear OC0A at TOP