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型號(hào)：	MQ83C154XXX-30P883D
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁(yè)數(shù)：	37/963頁(yè)
文件大?。?/td>	11933K
代理商：	MQ83C154XXX-30P883D

32142D–06/2013

ATUC64/128/256L3/4U

KILLBK: Kill IN Bank

This bit is cleared by hardware after the completion of the “kill packet procedure”.

This bit is set when the KILLBKS bit is written to one, killing the last written bank.

The user shall wait for this bit to be cleared before trying to process another IN packet.

Caution: The bank is cleared when the “kill packet” procedure is completed by the USBC core:

If the bank is really killed, the NBUSYBK field is decremented.

If the bank sent instead of killed (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case

can occur if an IN token comes while the user tries to kill the bank.

Note: If two banks are ready to be sent, the above specific case will not occur, since the first bank is sent (IN transfer) while the

last bank is killed.

NBUSYBKE: Number of Busy Banks Interrupt Enable

This bit is cleared when the NBUSYBKEC bit is written to zero, disabling the Number of Busy Banks interrupt (NBUSYBK).

This bit is set when the NBUSYBKES bit is written to one, enabling the Number of Busy Banks interrupt (NBUSYBK).

RAMACERE: RAMACER Interrupt Enable

This bit is cleared when the RAMACEREC bit is written to one, disabling the RAMACER interrupt (RAMACERI).

This bit is set when the RAMACERES bit is written to one, enabling the RAMACER interrupt (RAMACERI).

STALLEDE: STALLed Interrupt Enable

This bit is cleared when the STALLEDEC bit is written to one, disabling the STALLed interrupt (STALLEDI).

This bit is set when the STALLEDES bit is written to one, enabling the STALLed interrupt (STALLEDI).

CRCERRE: CRC Error Interrupt Enable

This bit is cleared when the CRCERREC bit is written to one, disabling the CRC Error interrupt (CRCERRI).

This bit is set when the CRCERRES bit is written to one, enabling the CRC Error interrupt (CRCERRI).

NAKINE: NAKed IN Interrupt Enable

This bit is cleared when the NAKINEC bit is written to one, disabling the NAKed IN interrupt (NAKINI).

This bit is set when the NAKINES bit is written to one, enabling the NAKed IN interrupt (NAKINI).

NAKOUTE: NAKed OUT Interrupt Enable

This bit is cleared when the NAKOUTEC bit is written to one, disabling the NAKed OUT interrupt (NAKOUTI).

This bit is set when the NAKOUTES bit is written to one, enabling the NAKed OUT interrupt (NAKOUTI).

RXSTPE: Received SETUP Interrupt Enable

This bit is cleared when the RXSTPEC bit is written to one, disabling the Received SETUP interrupt (RXSTPI).

This bit is set when the RXSTPES bit is written to one, enabling the Received SETUP interrupt (RXSTPI).

ERRORFE: Errorflow Interrupt Enable

This bit is cleared when the ERRORFEC bit is written to one, disabling the Underflow interrupt (ERRORFI).

This bit is set when the ERRORFES bit is written to one, enabling the Underflow interrupt (ERRORFI).

RXOUTE: Received OUT Data Interrupt Enable

This bit is cleared when the RXOUTEC bit is written to one, disabling the Received OUT Data interrupt (RXOUT).

This bit is set when the RXOUTES bit is written to one, enabling the Received OUT Data interrupt (RXOUT).

TXINE: Transmitted IN Data Interrupt Enable

This bit is cleared when the TXINEC bit is written to one, disabling the Transmitted IN Data interrupt (TXINI).

This bit is set when the TXINES bit is written to one, enabling the Transmitted IN Data interrupt (TXINI).

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