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型號：	MQ83C154XXX-30P883D
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁數(shù)：	526/963頁
文件大?。?/td>	11933K
代理商：	MQ83C154XXX-30P883D

32142D–06/2013

ATUC64/128/256L3/4U

enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of

data bytes in the transmission, including the PEC byte.

The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave

will leave the bus. The SR.SMBTOUT bit is also set.

A slave can get the master’s attention by pulling the SMBALERT line low. This is done by writing

a one to the SMBus Alert (SMBALERT) bit in CR. This will also enable address match on the

Alert Response Address (ARA).

Wakeup from Sleep Modes by TWI Address Match

The TWIS is able to wake the device up from a sleep mode upon an address match, including

sleep modes where CLK_TWIS is stopped. After detecting the START condition on the bus, The

TWIS will stretch TWCK until CLK_TWIS has started. The time required for starting CLK_TWIS

depends on which sleep mode the device is in. After CLK_TWIS has started, the TWIS releases

its TWCK stretching and receives one byte of data on the bus. At this time, only a limited part of

the device, including the TWIS, receives a clock, thus saving power. The TWIS goes on to

receive the slave address. If the address phase causes a TWIS address match, the entire

device is wakened and normal TWIS address matching actions are performed. Normal TWI

transfer then follows. If the TWIS is not addressed, CLK_TWIS is automatically stopped and the

device returns to its original sleep mode.

Identifying Bus Events

This chapter lists the different bus events, and how these affects the bits in the TWIS registers.

This is intended to help writing drivers for the TWIS.

Table 23-5.

Slave transmitter has sent a

SR.THR is cleared.

SR.BTF is set.

The value of the ACK bit sent immediately after the data byte is given

Slave receiver has received

SR.RHR is set.

SR.BTF is set.

SR.NAK updated according to value of ACK bit received from master.

Start+Sadr on bus, but

address is to another slave

Start+Sadr on bus, current

slave is addressed, but

address match enable bit in

CR is not set

Start+Sadr on bus, current

slave is addressed,

corresponding address

match enable bit in CR set

Correct address match bit in SR is set.

SR.TRA updated according to transfer direction (updating is done one

CLK_TWIS cycle after address match bit is set)

Slave enters appropriate transfer direction mode and data transfer

can commence.

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