![](http://datasheet.mmic.net.cn/30000/MR80C52CXXX-20SCR_datasheet_2377250/MR80C52CXXX-20SCR_93.png)
93
32142D–06/2013
ATUC64/128/256L3/4U
8.6.2.12
Multi packet mode and single packet mode.
Single packet mode is the default mode where one USB packet is managed per bank.
The multi-packet mode allows the user to manage data exceeding the maximum endpoint size
(UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention.
This mode can also be coupled with the ping-pong mode.
For an OUT endpoint, the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE field should be
initialized to 0.
For an IN endpoint, the EPn_PCKSIZE_BK0/1.BYTE_COUNT field should be configured
96. For single packet mode, the BYTE_COUNT should be less than EPSIZE.
8.6.2.13
Management of control endpoints
Overview
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn is irrelevant for control endpoints. The user should
therefore never use it for these endpoints. When read, this value is always zero.
Control endpoints are managed using:
The RXSTPI bit: is set when a new SETUP packet is received. This has to be cleared by
firmware in order to acknowledge the packet and to free the bank.
The RXOUTI bit: is set when a new OUT packet is received. This has to be cleared by
firmware in order to acknowledge the packet and to free the bank.
The Transmitted IN Data Interrupt (TXINI) bit: is set when the current bank is ready to accept
a new IN packet. This has to be cleared by firmware in order to send the packet.
Control write
will not necessarily send a NAK on the first IN token:
If the user knows the exact number of descriptor bytes that will be read, the status stage can
be predicted, and a zero-length packet can be sent after the next IN token.
Alternatively the bytes can be read until the NAKed IN Interrupt (NAKINI) is triggered,
notifying that all bytes are sent by the host and that the transaction is now in the status stage.